[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/cannonlake,skylake: Fix locking SMRAM

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83728?usp=email )

Change subject: soc/intel/cannonlake,skylake: Fix locking SMRAM
......................................................................

soc/intel/cannonlake,skylake: Fix locking SMRAM

Intel TXT SINIT required the D_LCK bit set. Although coreboot
tries to set it, the bit ws still clear. The D_LCK bit has to be
set using I/O CF8/CFC cycle.

TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled

Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c
Signed-off-by: Michał Żygowski 
---
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/skylake/cpu.c
2 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/83728/1

diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index b8a2c8c..53757f5 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -162,14 +162,14 @@

void smm_lock(void)
 {
-	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
    /*
     * LOCK the SMM memory window and enable normal SMM.
     * After running this function, only a full reset can
-	 * make the SMM registers writable again.
+	 * make the SMM registers writable again. D_LCK bit
+	 * requires the PCI 0xcf8/0xcfc I/O access.
     */
    printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 }

static void post_mp_init(void)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 5cf48ea..057aece 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -164,14 +164,14 @@

void smm_lock(void)
 {
-	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
    /*
     * LOCK the SMM memory window and enable normal SMM.
     * After running this function, only a full reset can
-	 * make the SMM registers writable again.
+	 * make the SMM registers writable again. D_LCK bit
+	 * requires the PCI 0xcf8/0xcfc I/O access.
     */
    printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 }

static void vmx_configure(void *unused)