John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43657 )
Change subject: soc/intel/tigerlake: Disable VT-d and no DMAR table for ES platform ......................................................................
soc/intel/tigerlake: Disable VT-d and no DMAR table for ES platform
This change disables VT-d support and no DMAR table generation for ES platform. VT-d and DMAR ACPI table will only be supported for other platforms like QS.
BUG=b:152242800,161215918 TEST=Validated VT-d is disabled for ES(cpu:0x806c0) and enabled for QS(cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled and no DMAR table exists, IOMMU will not be enabled.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 21 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43657/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 662ca06..2d7c05f 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include <cpu/x86/msr.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> #include <soc/msr.h> @@ -17,7 +18,7 @@ const struct soc_intel_tigerlake_config *config) { unsigned int i; - uint32_t mask = 0; + uint32_t cpu_id, mask = 0; const struct device *dev;
dev = pcidev_path_on_root(SA_DEVFN_IGD); @@ -182,18 +183,25 @@ sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
/* Vt-D config */ - m_cfg->VtdDisable = 0; - m_cfg->VtdIgdEnable = 0x1; - m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; - m_cfg->VtdIpuEnable = 0x1; - m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; - m_cfg->VtdIopEnable = 0x1; - m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; - m_cfg->VtdItbtEnable = 0x1; - m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; - m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; - m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; - m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_TIGERLAKE_A0) { + /* Disable Vt-D support for ES platform */ + m_cfg->VtdDisable = 1; + } else { + /* Enable Vt-D support for other platforms */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdIopEnable = 0x1; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->VtdItbtEnable = 0x1; + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; + }
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);