[coreboot-gerrit] Change in ...coreboot[master]: soc/amd/picasso: Add code to support Romstage in RAM

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32415 )

Change subject: soc/amd/picasso: Add code to support Romstage in RAM
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Patch Set 1:

Could you add some documentation about what stages are run, in what sort of environment and what they do?
I have a few questions about the bootflow.
The reset vector is in a romstage located in RAM?
Is there a possibility to chose where it executes and who puts it in ram?
What should the romstage do besides initializing cbmem and loading ramstage?

Also, is there some public documentation?