Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21641
Change subject: mb/intel/dg43gt: Fix very long boot delays with USE_OPTION_TABLE ......................................................................
mb/intel/dg43gt: Fix very long boot delays with USE_OPTION_TABLE
With USE_OPTION_TABLE console_init() will fetch both baudrate and debug level from rtc nvram. These functions will at some point try to create some output even though console is not ready yet.
This board seems to have the COMA hardware in an undefined state with a very low divisor which results in long boot delay ~30s. Setting the BDLAB bit seems to fix it.
Change-Id: I6a23ef9577161084521b569fc3870a27f50624d1 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/intel/dg43gt/romstage.c 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/21641/1
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 6944b18..b84f5a2 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -26,6 +26,7 @@ #include <lib.h> #include <northbridge/intel/x4x/iomap.h> #include <timestamp.h> +#include <drivers/uart/uart8250reg.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) @@ -83,6 +84,15 @@ mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ /* Aparantly the COMA port is booted in an undefined state in which + * the divisor is very high. In console_init() some functions are + * called which print to the console resulting in very long + * (up to 30s) boot delays. + * Setting the Baudrate Divisor Latch Access Bit (BDLAB) here fixes it. + */ + if (CONFIG_TTYS0_BASE == 0x3f8) + outb(UART8250_LCR_DLAB, CONFIG_TTYS0_BASE + UART8250_LCR); + console_init();
report_bist_failure(bist);