[coreboot-gerrit] [L] Change in coreboot[main]: mb/google/fatcat: Add GPIO settings

[Wonkyu Kim (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Pranava Y N, Subrata Banik.

Wonkyu Kim has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84405?usp=email )

Change subject: mb/google/fatcat: Add GPIO settings
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Patch Set 6:

(2 comments)

File src/mainboard/google/fatcat/variants/fatcat/gpio.c:

https://review.coreboot.org/c/coreboot/+/84405/comment/0551dc02_f3b007ac?usp... :
PS1, Line 9: static const struct pad_config gpio_table[] = {
Can we use different files for bootblock, romstage and ramstage so that we can reduce RO size and Romstage size?  As each stage use its only it's table, each stage will have unused pin mux table.

https://review.coreboot.org/c/coreboot/+/84405/comment/e89fbe00_519cd966?usp... :
PS1, Line 427: 	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
             : 	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
             :
> > Subrata, we don't use fw_config in early and romstage for our PTL and SoCs in the past. […]

I also think bootblock pin mux should be minimal.

Cliff, let's move feature related to pin mux from boot block to romstage.
And from romstage, it's better use fw_config for feature pin mux so that we can only configure when the HW feature is used.