Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Ren Kuo.
Subrata Banik has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email )
Change subject: mb/google/brox/jubilant: Update GPE0 routing ......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brox/variants/jubilant/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84124/comment/f5e7ec3d_dc66be98?usp... : PS4, Line 25: register "pmc_gpe0_dw1" = "GPP_F"
if wake sources are scattered across more than 3 GPIO bank then you can use GPIO Tier 1 register to add additional entries.
I am not seeing any precedence for that. Also chip config does not seem to support more than 3 entries. It seems we need to configure PMC as well as GPIO communities for every tier. Should I ask Intel's support on this one?
Here is my understanding (I misspoke in my previous reply, the GPIOs in question are referred to as Tier 2 GPIOs). There are two ways to configure GPIO events.
1. Using Tier 1, we can configure up to 3 GPIO banks. 2. We can configure those banks as SCI, which allows them to generate GPE. There are GPE registers 0-127, of which 0-95 are configurable and 96-127 are generic. 3. If we need more GPIOs to be configured as GPE, we need to move them to GPIO Tier 2 programming. I don't see the register details for this in the EDS, but I believe you can ask Intel for information on how to configure additional PADs as Tier 2 GPIOs to register GPE. 4. The Tier 2 GPEs are considered a MUX'ed GPE, where General Purpose Event 0 Status [127:96] register bit 15 is used for GPIO_TIER2_SCI_STATUS (and GPIO_TIER2_SCI_EN likewise).
``` GPIO Tier2 SCI EN (GPIO_TIER2_SCI_EN)
Used to enable the setting of GPIO_TIER2_SCI_STS to generate wake/SCI#. ```