Attention is currently required from: Maulik V Vaghela, Jonathan Zhang, Angel Pons, Sridhar Siricilla, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Nick Vaccaro, Werner Zeh, Tim Chu. Hello build bot (Jenkins), Maulik V Vaghela, Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Nick Vaccaro, Werner Zeh, EricR Lai, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61431
to look at the new patch set (#8).
Change subject: soc/intel/common/cse: Rework heci_disable function ......................................................................
soc/intel/common/cse: Rework heci_disable function
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure.
Finally, rename heci_disable() function to heci1_disable() to make it more meaningful.
BUG=none TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 --- M src/soc/intel/alderlake/smihandler.c M src/soc/intel/apollolake/include/soc/pcr_ids.h M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/elkhartlake/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/tigerlake/smihandler.c M src/soc/intel/xeon_sp/include/soc/pcr_ids.h 13 files changed, 78 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/8