[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

[Shuo Liu (Code Review)]

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, [e-mail].

Shuo Liu has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )

Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 15:

(7 comments)

File src/soc/intel/snowridge/acpi.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/d66d1020_8e5045f4?usp... :
PS15, Line 97: {
maybe the common codes could be used (src/acpi/acpigen_pci_root_resource_producer.c)

https://review.coreboot.org/c/coreboot/+/83321/comment/5cc43e20_196485cf?usp... :
PS15, Line 168: 	if (dev->path.type != DEVICE_PATH_DOMAIN ||
could use domain0 checker here.

https://review.coreboot.org/c/coreboot/+/83321/comment/a18687c1_c3788585?usp... :
PS15, Line 174: 	uncore_fill_ssdt();
uncore usually indicates northcluster, a bit confusing here.

https://review.coreboot.org/c/coreboot/+/83321/comment/70222886_dc5b3c0a?usp... :
PS15, Line 243: 		if (read32p(HPET_BASE_ADDRESS + 0x100) & 0x00008000) {
are there macros for these constants?

https://review.coreboot.org/c/coreboot/+/83321/comment/536997cb_53d64da8?usp... :
PS15, Line 277: 		} else if (stack == STACK2) {
there includes some hardcodings, not sure if this could improved in future. e.g. to generate this based on pci enum results.

https://review.coreboot.org/c/coreboot/+/83321/comment/4538833f_9c0b5d68?usp... :
PS15, Line 430: 	if (dev->upstream->secondary) /**< Write only for system agent in the first domain 0. */
could use the domain0 checker

File src/soc/intel/snowridge/sriov.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/d86ea559_661fa090?usp... :
PS15, Line 12: 
not sure if this could be moved to common pci codes.