[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: set power limits dynamically for thermal

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57462 )

Change subject: mb/intel/adlrvp: set power limits dynamically for thermal
......................................................................

mb/intel/adlrvp: set power limits dynamically for thermal

Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
These values are as per platform design specification.

BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board

Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5
Signed-off-by: Sumeet Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/adlrvp/ramstage.c
2 files changed, 11 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index bc2a57e..bd67192 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -40,6 +40,7 @@
 void variant_devtree_update(void);
 struct cpu_power_limits {
    uint16_t mchid;
+	u8 cpu_tdp;
    unsigned int pl1_min_power;
    unsigned int pl1_max_power;
    unsigned int pl2_min_power;
diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c
index 99ce52e..76cf53a 100644
--- a/src/mainboard/intel/adlrvp/ramstage.c
+++ b/src/mainboard/intel/adlrvp/ramstage.c
@@ -10,14 +10,16 @@
 #include <soc/soc_chip.h>
 #include <drivers/intel/dptf/chip.h>
 #include "board_id.h"
+#include <intelblocks/power_limit.h>

const struct cpu_power_limits limits[] = {
-	/* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max */
    /* PL2 values are for performance configuration */
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000,  55000,  55000 },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 3000, 15000,  55000,  55000 },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000,  64000,  64000 },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 115000, 115000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000,  55000,  55000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000,  55000,  55000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000,  64000,  64000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000,  64000,  64000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000 },
 };

WEAK_DEV_PTR(dptf_policy);
@@ -31,8 +33,10 @@

uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);

+	u8 tdp = get_cpu_tdp();
+
    for (size_t i = 0; i < ARRAY_SIZE(limits); i++) {
-		if (mchid == limits[i].mchid) {
+		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
    		struct dptf_power_limits *settings = &config->controls.power_limits;
    		settings->pl1.min_power = limits[i].pl1_min_power;
    		settings->pl1.max_power = limits[i].pl1_max_power;