Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74296 )
Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled ......................................................................
soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
Processor attached memory should not use reserved_ram_from_to and treat the calculation of gi_mem_size size as 64MB.
By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Before the fix running command 'free -g -h' under Linux shows the total memory is only 1.4Gi, after the fix it's showing the expected total memory size 15Gi.
Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. On OCP Crater Lake with CXL memory attached, CXL memory can be recognized in NUMA node 1: numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 .. 59 node 0 size: 95854 MB node 0 free: 93860 MB node 1 cpus: node 1 size: 63488 MB node 1 free: 63488 MB node distances: node 0 1 0: 10 14 1: 14 10
Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296 Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-by: Shuo Liu shuo.liu@intel.com Reviewed-by: Johnny Lin Johnny_Lin@wiwynn.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 54 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 5249a94..3744359 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -249,10 +249,16 @@ if (CONFIG(SOC_INTEL_HAS_CXL)) { /* 4GiB -> CXL Memory */ uint32_t gi_mem_size; - gi_mem_size = get_generic_initiator_mem_size(); - - res = reserved_ram_from_to(dev, index++, 0x100000000, - mc_values[TOHM_REG] - (uint64_t)gi_mem_size + 1); + gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ + /* + * Memory layout when there is CXL HDM (Host-managed Device Memory): + * -------------- <- TOHM + * CXL memory regions (pds global variable records the base/size of them) + * Processor attached high memory + * -------------- <- 0x100000000 (4GB) + */ + res = upper_ram_end(dev, index++, + mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); LOG_RESOURCE("high_ram", dev, res);
/* CXL Memory */ @@ -269,8 +275,9 @@ else flags |= IORESOURCE_STORED;
- res = fixed_mem_range_flags(dev, index++, (uint64_t)pds.pds[i].base, - (uint64_t)pds.pds[i].size, flags); + res = fixed_mem_range_flags(dev, index++, + (uint64_t)pds.pds[i].base << 26, + (uint64_t)pds.pds[i].size << 26, flags); if (cxl_mode == CXL_SPM) LOG_RESOURCE("specific_purpose_memory", dev, res); else