Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3895
-gerrit
commit d1b415af98b79c621e75eb3d762b4d483dce80a2 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Tue Sep 3 05:25:57 2013 +0300
CBMEM AMD: Fix calls to set_top_of_ram_once()
We can postpone the call to set_top_of_ram_once() outside the loops and make just one call instead.
As set_top_of_ram() is now only called once, it is no longer necessary to check if high_tables_base was already set.
Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/x86/boot/cbmem.c | 8 +++----- src/include/cbmem.h | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family12/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family14/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family16kb/northbridge.c | 18 ++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 19 ++++++++----------- src/northbridge/amd/amdk8/northbridge.c | 18 ++++++++---------- 10 files changed, 68 insertions(+), 87 deletions(-)
diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 888c1f4..3f738be 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -23,12 +23,10 @@ * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. */ -void set_top_of_ram_once(uint64_t ramtop) +void set_top_of_ram(uint64_t ramtop) { - if (high_tables_base == 0) { - high_tables_base = ramtop - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - } + high_tables_base = ramtop - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index fe960d7..00d74d6 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -136,7 +136,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem);
#ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; -void set_top_of_ram_once(uint64_t ramtop); +void set_top_of_ram(uint64_t ramtop); void set_cbmem_toc(struct cbmem_entry *); #endif
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 602d473..1c7e547 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -914,6 +914,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1036,11 +1037,8 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -1057,15 +1055,15 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; }
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif
for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 4c230f1..42b4b3d 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -590,6 +590,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -722,11 +723,8 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -743,16 +741,16 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif
for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index fbf8e44..7cc812b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -575,6 +575,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -716,11 +717,8 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -737,16 +735,16 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif
for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index bdd6939..a8cc1cc 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -684,6 +684,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -807,11 +808,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -828,15 +826,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; }
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif
for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 736e634..b55d52b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -671,6 +671,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -793,11 +794,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -815,15 +813,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; }
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif
for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 266319c..b8bba50 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,6 +677,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -799,11 +800,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -821,15 +819,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; }
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif
for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8dbb480..6bcab41 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -877,6 +877,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1037,12 +1038,8 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1070,15 +1067,15 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; }
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif
for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c7321a4..8f0a11b 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -874,6 +874,7 @@ static void amdk8_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; @@ -1042,11 +1043,8 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1071,15 +1069,15 @@ static void amdk8_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; }
#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif assign_resources(dev->link_list);