Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62703 )
Change subject: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage ......................................................................
mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Program BayHub eMMC enable pin in ram stage to prevent baseboad override the setting leads RTD3 not able to control when enter and exit suspend state.
BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage scope enable pin while performing suspend stress and enable pin works as expected. test suspend stress 100 cycles passed on primus.
Signed-off-by: Casper Chang casper_chang@wistron.corp-partner.google.com Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62703/1
diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index d4d6684..c224866 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -49,6 +49,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE),
diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index d2dadc3..5947b6e 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -53,6 +53,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE),