[coreboot-gerrit] Change in ...coreboot[master]: soc/cavium/cn81xx: Enable RNG for DRAM init

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31567 )

Change subject: soc/cavium/cn81xx: Enable RNG for DRAM init
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Patch Set 2: Code-Review+2

(2 comments)

https://review.coreboot.org/#/c/31567/2/src/soc/cavium/cn81xx/sdram.c 
File src/soc/cavium/cn81xx/sdram.c:

https://review.coreboot.org/#/c/31567/2/src/soc/cavium/cn81xx/sdram.c@44 
PS2, Line 44: #if ENV_ROMSTAGE
Acceptable, I just like it more when "raminit" is only built for romstage.

https://review.coreboot.org/#/c/31567/2/src/soc/cavium/cn81xx/sdram.c@67 
PS2, Line 67: 	/* Read back after enable so we know it is done. */
You don't need to poll any bits here know it's ready to accept the reads below? As printk() had some delay, run some test to make sure the 3rd read value is still properly random after loglevel change.