Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3793
-gerrit
commit d023b9bd073d0907293dfa22cb9969e95e6de2eb Author: Damien Zammit damien@zamaudio.com Date: Sat Jul 20 03:30:32 2013 +1000
NOTFORMERGE: Added early serial superio init & fixed reboot loop.
Serial console debug still not outputting anything. However reboot loop has ceased now that undocumented GPIO register is set properly.
Change-Id: Ic249ae68e728b138ffd72b9456c4b3801515229d Signed-off-by: Damien Zammit damien@zamaudio.com --- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index ca7db44..f2bc78e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -30,9 +30,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> - #include <delay.h>
+#include "superio/ite/it8728f/early_serial.c" + #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" #include "southbridge/intel/bd82x6x/pch.h" @@ -200,14 +201,18 @@ void main(unsigned long bist)
pch_enable_lpc();
+ /* Initialize SuperIO */ + it8728f_enable_serial(0, CONFIG_TTYS0_BASE); + it8728f_disable_reboot(); + + /* Initialize console device(s) */ + console_init(); + /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&b75md3v_gpio_map);
- /* Initialize console device(s) */ - console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist);