Attention is currently required from: Nico Huber, Tim Wawrzynczak, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46959 )
Change subject: sb/intel/lynxpoint/acpi: Add missing USB ports ......................................................................
Patch Set 11:
(1 comment)
File src/southbridge/intel/lynxpoint/acpi/xhci.asl:
https://review.coreboot.org/c/coreboot/+/46959/comment/be310c5c_6c358278 PS11, Line 346: Device (SSP6) { Name (_ADR, 15) } // USB Port 15 Yeah, and 486708 Rev2.0 section `5.21 xHCI Controller (D20:F0)` also says the following:
Some USB 3.0 motherboard down devices do not require support for USB 2.0 speed and it is possible to route only the SuperSpeed signals, as allowed by the USB 3.0 specification. In this special case, USB 2.0 and USB 3.0 signals will not need to be paired together, thereby allowing support for more than 14 USB connections.
This means there can be more than 14 USB ports in some cases, though I would expect this to be a highly unusual configuration. Moreover, the number of USB ports depends on PCH-H vs PCH-LP (known at compile-time), and also on HSIO configuration (mainboard-specific).
I've primarily added these devices to synchronize with Broadwell ASL, since I want to unify them someday.
Maybe I should move the USB settings from romstage to the devicetree, and use that to create the device nodes through acpigen. This would also allow decoupling USB settings from pei_data.h (the MRC ABI), which is desired because Haswell and Broadwell MRCs have incompatible ABIs. And since I don't need to use the Haswell MRC anymore, not depending on its ABI is also a plus. But this would be best done separately.