[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO high range

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Nico Huber has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83538?usp=email )

Change subject: soc/intel/xeon_sp: Reserve MMIO high range
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Patch Set 4: Code-Review+1

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83538/comment/012841b7_9d174b70?usp... :
PS1, Line 7: soc/intel/xeon_sp: Reserve FSP MMIO high window
> For 'non PCI domain MMIOs', they are used for misc devices belonged to an IIO stack but not belonged to any PCIe domains under that stack. For Gen6, VTd BAR is counted to this class, similarly is the CXL host bridge control register BAR.

What I don't get: Are these resources not known to coreboot? If they are known,
they shouldn't cause segmentation. If they are not known to coreboot, that's a bug.