Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45096 )
Change subject: vc/amd/fsp/picasso: Update to UPD 1.0.1.3 ......................................................................
vc/amd/fsp/picasso: Update to UPD 1.0.1.3
BUG=b:159823235 TEST=Build test
Cq-Depend: chrome-internal:3251807 Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2 --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45096/1
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 5adbb81..b9f9a3b 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -15,7 +15,8 @@
typedef struct __packed { /** Offset 0x0020**/ uint32_t emmc0_mode; - /** Offset 0x0024**/ uint8_t unused0[12]; + /** Offset 0x0024**/ uint8_t emmc0_drive_strength; + /** Offset 0x0025**/ uint8_t unused0[11]; /** Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][16]; /** Offset 0x00B0**/ uint8_t unused1[16]; /** Offset 0x00C0**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT]; @@ -31,7 +32,8 @@ /** Offset 0x011D**/ uint8_t unused3; /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; /** Offset 0x0122**/ uint8_t xhci0_force_gen1; - /** Offset 0x0123**/ uint8_t UnusedUpdSpace0[45]; + /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x0124**/ uint8_t UnusedUpdSpace0[44]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG;