[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add postcar_frame_common_mtrrs()

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Huang Jin, Lee Leahy, build bot (Jenkins), Damien Zammit,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34809

to look at the new patch set (#3).

Change subject: arch/x86: Add postcar_frame_common_mtrrs()
......................................................................

arch/x86: Add postcar_frame_common_mtrrs()

As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.

Add possibility for the platform to skip these if
required.

Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki 
---
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/postcar_loader.c
M src/cpu/intel/car/romstage.c
M src/drivers/intel/fsp1_1/car.c
M src/northbridge/intel/e7505/memmap.c
M src/northbridge/intel/gm45/memmap.c
M src/northbridge/intel/haswell/memmap.c
M src/northbridge/intel/i440bx/memmap.c
M src/northbridge/intel/i945/memmap.c
M src/northbridge/intel/nehalem/memmap.c
M src/northbridge/intel/pineview/memmap.c
M src/northbridge/intel/sandybridge/memmap.c
M src/northbridge/intel/x4x/memmap.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/romstage/romstage.c
15 files changed, 24 insertions(+), 74 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34809/3