Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83838?usp=email )
Change subject: Add starfive visionfive2 mainboard ......................................................................
Add starfive visionfive2 mainboard
tested:
not working:
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: I029ac83d374b23ad522c7dd3777923afb094e6d1 --- M Documentation/acronyms.md M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk A src/arch/riscv/include/dt-bindings/clock/starfive,jh7110-crg.h A src/arch/riscv/include/dt-bindings/gpio/gpio.h A src/arch/riscv/include/dt-bindings/power/starfive,jh7110-pmu.h A src/arch/riscv/include/dt-bindings/reset/starfive,jh7110-crg.h A src/arch/riscv/include/dt-bindings/thermal/thermal.h M src/lib/device_tree.c A src/mainboard/starfive/Kconfig A src/mainboard/starfive/Kconfig.name A src/mainboard/starfive/visionfive2/Kconfig A src/mainboard/starfive/visionfive2/Kconfig.name A src/mainboard/starfive/visionfive2/board_info.txt A src/mainboard/starfive/visionfive2/bootblock.c A src/mainboard/starfive/visionfive2/cbfs_spi.c A src/mainboard/starfive/visionfive2/devicetree.cb A src/mainboard/starfive/visionfive2/dts/move-dts.sh A src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.2a.dts A src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.3b.dts A src/mainboard/starfive/visionfive2/dts/visionfive-2.dtsi A src/mainboard/starfive/visionfive2/fixup_fdt.c A src/mainboard/starfive/visionfive2/mainboard.c A src/mainboard/starfive/visionfive2/romstage.c A src/soc/starfive/jh7110/Kconfig A src/soc/starfive/jh7110/bootblock.c A src/soc/starfive/jh7110/cbmem.c A src/soc/starfive/jh7110/chip.c A src/soc/starfive/jh7110/clint.c A src/soc/starfive/jh7110/clock_reset.c A src/soc/starfive/jh7110/gpio.c A src/soc/starfive/jh7110/include/soc/addressmap.h A src/soc/starfive/jh7110/include/soc/clock.h A src/soc/starfive/jh7110/include/soc/gpio.h A src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h A src/soc/starfive/jh7110/include/soc/jh7110.dtsi A src/soc/starfive/jh7110/include/soc/sdram.h A src/soc/starfive/jh7110/memlayout.ld A src/soc/starfive/jh7110/sdram.c A src/soc/starfive/jh7110/uart.c A util/riscv/starfive-jh7110-spl-tool/.gitignore A util/riscv/starfive-jh7110-spl-tool/LICENSE A util/riscv/starfive-jh7110-spl-tool/Makefile A util/riscv/starfive-jh7110-spl-tool/README.md A util/riscv/starfive-jh7110-spl-tool/SOURCE A util/riscv/starfive-jh7110-spl-tool/crc32.c A util/riscv/starfive-jh7110-spl-tool/spl_tool.c 47 files changed, 8,112 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83838/1
diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 8dbb067..18067e7 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -18,6 +18,7 @@ initialization that happens from the PSP. Significantly, Memory Initialization. * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current) +* ACE - AXI Coherency Extensions * Ack - Acknowledgment / Acknowledged * ACM – [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html) * ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power) @@ -56,11 +57,14 @@ * AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology) * ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Institute) * AOAC - AMD: Always On, Always Connected +* AON - Always ON: Sometimes used for power domains that are always on (e.g. RTC, GPIOs, Wake on LAN ...) * AP - Application processor - The main processor on the board (as opposed to the embedded controller or other processors that may be on the system), any cores in the processor chip that aren't the BSP (Boot Strap Processor). +* APB - Advanced Peripheral Bus (part of the AMBA bus specification) * APCB - AMD: AMD PSP Customization Block +* AHB - Advanced High-performance Bus (part of the AMBA bus specification) * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API) * APIC - [**Advanced Programmable Interrupt Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller) @@ -94,7 +98,7 @@ * ATAPI - [**ATA Packet Interface**](https://en.wikipedia.org/wiki/Parallel_ATA#ATAPI) * ATX - [**Advanced Technology eXtended**](https://en.wikipedia.org/wiki/ATX) * AVX - [**Advanced Vector Extensions**](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions) - +* AXI - [Advanced eXtensible Interface](https://en.wikipedia.org/wiki/Advanced_eXtensible_Interface) part of the AMBA bus specification
## B
@@ -169,6 +173,7 @@ * CDN - [**Content Delivery Network**](https://en.wikipedia.org/wiki/Content_delivery_network) * CEM - PCIe: [**Card ElectroMechanical**](https://members.pcisig.com/wg/PCI-SIG/document/folder/839) specification * CFL - [**Coffee Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake) +* CHI - Coherent Hub Interface * CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity) * CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim) * CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer) @@ -517,6 +522,7 @@ processor to help offload data processing from various sensors on a mainboard. * ISP - Internet Service Provider +* ISP - Image-Signal-Process * IVHD - ACPI: I/O Virtualization Hardware Definition * IVMD - ACPI: I/O Virtualization Memory Definition * IVRS - I/O Virtualization Reporting Structure @@ -990,6 +996,7 @@ * SSPHY - USB: USB3 Super-Speed PHY * STAPM - AMD: Skin Temperature Aware Power Management * STB - AMD: Smart Trace Buffer +* STG - System-Top-Group apparently a term for grouping subsystems in an SOC together? TODO * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O) (SIO) device provides a system with any of a number of different peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 5d887ea..d59026f 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -135,4 +135,19 @@ bool default y
+config RISCV_DTS + bool + default n + help + This option is selected by mainboards that include a devicetree + source file (not to be confused with the coreboot devicetree.cb files). + The devicetree will be preprocessed and compiled into a FDT (flattened devicetree). + Said FDT will be put into a CBFS file for use in runtime. + +config RISCV_DTS_FILE + string + depends on RISCV_DTS + help + Path to the devicetree source file in .dts format. + endif # if ARCH_RISCV diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index be8962a..9854096 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -67,6 +67,28 @@ $(top)/src/lib/memset.c all-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
+## FDT (Flattened Devicetree) inclusion + +ifeq ($(CONFIG_RISCV_DTS),y) + +## at some point dtc may be compiled by our toolchain +DTC ?= dtc +CPPFLAGS_dts += -nostdinc -P -x assembler-with-cpp -I src/arch/riscv/include + +$(obj)/preprocessed.dts: $(call strip_quotes, $(CONFIG_RISCV_DTS_FILE)) + $(CPP_riscv) $(CPPFLAGS_dts) -o $@ $< + +$(obj)/dtb: $(obj)/preprocessed.dts + $(DTC) -I dts -O dtb -o $@ $< + +## This may be optimized in the future by letting cbfstool parse our FDT into a unflattened +## devicetree blob in build time, so that we only need to flatten it in runtime instead of +## unflatten and flatten it in runtime. +cbfs-files-y += FDT +FDT-file := $(obj)/dtb +FDT-type := raw + +endif # CONFIG_RISCV_DTS
################################################################################ ## bootblock diff --git a/src/arch/riscv/include/dt-bindings/clock/starfive,jh7110-crg.h b/src/arch/riscv/include/dt-bindings/clock/starfive,jh7110-crg.h new file mode 100644 index 0000000..467ccab --- /dev/null +++ b/src/arch/riscv/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2022 Emil Renner Berthing kernel@esmil.dk + * Copyright 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ + +/* PLL clocks */ +#define JH7110_PLLCLK_PLL0_OUT 0 +#define JH7110_PLLCLK_PLL1_OUT 1 +#define JH7110_PLLCLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + +/* SYSCRG clocks */ +#define JH7110_SYSCLK_CPU_ROOT 0 +#define JH7110_SYSCLK_CPU_CORE 1 +#define JH7110_SYSCLK_CPU_BUS 2 +#define JH7110_SYSCLK_GPU_ROOT 3 +#define JH7110_SYSCLK_PERH_ROOT 4 +#define JH7110_SYSCLK_BUS_ROOT 5 +#define JH7110_SYSCLK_NOCSTG_BUS 6 +#define JH7110_SYSCLK_AXI_CFG0 7 +#define JH7110_SYSCLK_STG_AXIAHB 8 +#define JH7110_SYSCLK_AHB0 9 +#define JH7110_SYSCLK_AHB1 10 +#define JH7110_SYSCLK_APB_BUS 11 +#define JH7110_SYSCLK_APB0 12 +#define JH7110_SYSCLK_PLL0_DIV2 13 +#define JH7110_SYSCLK_PLL1_DIV2 14 +#define JH7110_SYSCLK_PLL2_DIV2 15 +#define JH7110_SYSCLK_AUDIO_ROOT 16 +#define JH7110_SYSCLK_MCLK_INNER 17 +#define JH7110_SYSCLK_MCLK 18 +#define JH7110_SYSCLK_MCLK_OUT 19 +#define JH7110_SYSCLK_ISP_2X 20 +#define JH7110_SYSCLK_ISP_AXI 21 +#define JH7110_SYSCLK_GCLK0 22 +#define JH7110_SYSCLK_GCLK1 23 +#define JH7110_SYSCLK_GCLK2 24 +#define JH7110_SYSCLK_CORE 25 +#define JH7110_SYSCLK_CORE1 26 +#define JH7110_SYSCLK_CORE2 27 +#define JH7110_SYSCLK_CORE3 28 +#define JH7110_SYSCLK_CORE4 29 +#define JH7110_SYSCLK_DEBUG 30 +#define JH7110_SYSCLK_RTC_TOGGLE 31 +#define JH7110_SYSCLK_TRACE0 32 +#define JH7110_SYSCLK_TRACE1 33 +#define JH7110_SYSCLK_TRACE2 34 +#define JH7110_SYSCLK_TRACE3 35 +#define JH7110_SYSCLK_TRACE4 36 +#define JH7110_SYSCLK_TRACE_COM 37 +#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 +#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 +#define JH7110_SYSCLK_OSC_DIV2 40 +#define JH7110_SYSCLK_PLL1_DIV4 41 +#define JH7110_SYSCLK_PLL1_DIV8 42 +#define JH7110_SYSCLK_DDR_BUS 43 +#define JH7110_SYSCLK_DDR_AXI 44 +#define JH7110_SYSCLK_GPU_CORE 45 +#define JH7110_SYSCLK_GPU_CORE_CLK 46 +#define JH7110_SYSCLK_GPU_SYS_CLK 47 +#define JH7110_SYSCLK_GPU_APB 48 +#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 +#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 +#define JH7110_SYSCLK_ISP_TOP_CORE 51 +#define JH7110_SYSCLK_ISP_TOP_AXI 52 +#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 +#define JH7110_SYSCLK_HIFI4_CORE 54 +#define JH7110_SYSCLK_HIFI4_AXI 55 +#define JH7110_SYSCLK_AXI_CFG1_MAIN 56 +#define JH7110_SYSCLK_AXI_CFG1_AHB 57 +#define JH7110_SYSCLK_VOUT_SRC 58 +#define JH7110_SYSCLK_VOUT_AXI 59 +#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 +#define JH7110_SYSCLK_VOUT_TOP_AHB 61 +#define JH7110_SYSCLK_VOUT_TOP_AXI 62 +#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63 +#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64 +#define JH7110_SYSCLK_JPEGC_AXI 65 +#define JH7110_SYSCLK_CODAJ12_AXI 66 +#define JH7110_SYSCLK_CODAJ12_CORE 67 +#define JH7110_SYSCLK_CODAJ12_APB 68 +#define JH7110_SYSCLK_VDEC_AXI 69 +#define JH7110_SYSCLK_WAVE511_AXI 70 +#define JH7110_SYSCLK_WAVE511_BPU 71 +#define JH7110_SYSCLK_WAVE511_VCE 72 +#define JH7110_SYSCLK_WAVE511_APB 73 +#define JH7110_SYSCLK_VDEC_JPG 74 +#define JH7110_SYSCLK_VDEC_MAIN 75 +#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 +#define JH7110_SYSCLK_VENC_AXI 77 +#define JH7110_SYSCLK_WAVE420L_AXI 78 +#define JH7110_SYSCLK_WAVE420L_BPU 79 +#define JH7110_SYSCLK_WAVE420L_VCE 80 +#define JH7110_SYSCLK_WAVE420L_APB 81 +#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 +#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 +#define JH7110_SYSCLK_AXI_CFG0_MAIN 84 +#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85 +#define JH7110_SYSCLK_AXIMEM2_AXI 86 +#define JH7110_SYSCLK_QSPI_AHB 87 +#define JH7110_SYSCLK_QSPI_APB 88 +#define JH7110_SYSCLK_QSPI_REF_SRC 89 +#define JH7110_SYSCLK_QSPI_REF 90 +#define JH7110_SYSCLK_SDIO0_AHB 91 +#define JH7110_SYSCLK_SDIO1_AHB 92 +#define JH7110_SYSCLK_SDIO0_SDCARD 93 +#define JH7110_SYSCLK_SDIO1_SDCARD 94 +#define JH7110_SYSCLK_USB_125M 95 +#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 +#define JH7110_SYSCLK_GMAC1_AHB 97 +#define JH7110_SYSCLK_GMAC1_AXI 98 +#define JH7110_SYSCLK_GMAC_SRC 99 +#define JH7110_SYSCLK_GMAC1_GTXCLK 100 +#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 +#define JH7110_SYSCLK_GMAC1_PTP 102 +#define JH7110_SYSCLK_GMAC1_RX 103 +#define JH7110_SYSCLK_GMAC1_RX_INV 104 +#define JH7110_SYSCLK_GMAC1_TX 105 +#define JH7110_SYSCLK_GMAC1_TX_INV 106 +#define JH7110_SYSCLK_GMAC1_GTXC 107 +#define JH7110_SYSCLK_GMAC0_GTXCLK 108 +#define JH7110_SYSCLK_GMAC0_PTP 109 +#define JH7110_SYSCLK_GMAC_PHY 110 +#define JH7110_SYSCLK_GMAC0_GTXC 111 +#define JH7110_SYSCLK_IOMUX_APB 112 +#define JH7110_SYSCLK_MAILBOX_APB 113 +#define JH7110_SYSCLK_INT_CTRL_APB 114 +#define JH7110_SYSCLK_CAN0_APB 115 +#define JH7110_SYSCLK_CAN0_TIMER 116 +#define JH7110_SYSCLK_CAN0_CAN 117 +#define JH7110_SYSCLK_CAN1_APB 118 +#define JH7110_SYSCLK_CAN1_TIMER 119 +#define JH7110_SYSCLK_CAN1_CAN 120 +#define JH7110_SYSCLK_PWM_APB 121 +#define JH7110_SYSCLK_WDT_APB 122 +#define JH7110_SYSCLK_WDT_CORE 123 +#define JH7110_SYSCLK_TIMER_APB 124 +#define JH7110_SYSCLK_TIMER0 125 +#define JH7110_SYSCLK_TIMER1 126 +#define JH7110_SYSCLK_TIMER2 127 +#define JH7110_SYSCLK_TIMER3 128 +#define JH7110_SYSCLK_TEMP_APB 129 +#define JH7110_SYSCLK_TEMP_CORE 130 +#define JH7110_SYSCLK_SPI0_APB 131 +#define JH7110_SYSCLK_SPI1_APB 132 +#define JH7110_SYSCLK_SPI2_APB 133 +#define JH7110_SYSCLK_SPI3_APB 134 +#define JH7110_SYSCLK_SPI4_APB 135 +#define JH7110_SYSCLK_SPI5_APB 136 +#define JH7110_SYSCLK_SPI6_APB 137 +#define JH7110_SYSCLK_I2C0_APB 138 +#define JH7110_SYSCLK_I2C1_APB 139 +#define JH7110_SYSCLK_I2C2_APB 140 +#define JH7110_SYSCLK_I2C3_APB 141 +#define JH7110_SYSCLK_I2C4_APB 142 +#define JH7110_SYSCLK_I2C5_APB 143 +#define JH7110_SYSCLK_I2C6_APB 144 +#define JH7110_SYSCLK_UART0_APB 145 +#define JH7110_SYSCLK_UART0_CORE 146 +#define JH7110_SYSCLK_UART1_APB 147 +#define JH7110_SYSCLK_UART1_CORE 148 +#define JH7110_SYSCLK_UART2_APB 149 +#define JH7110_SYSCLK_UART2_CORE 150 +#define JH7110_SYSCLK_UART3_APB 151 +#define JH7110_SYSCLK_UART3_CORE 152 +#define JH7110_SYSCLK_UART4_APB 153 +#define JH7110_SYSCLK_UART4_CORE 154 +#define JH7110_SYSCLK_UART5_APB 155 +#define JH7110_SYSCLK_UART5_CORE 156 +#define JH7110_SYSCLK_PWMDAC_APB 157 +#define JH7110_SYSCLK_PWMDAC_CORE 158 +#define JH7110_SYSCLK_SPDIF_APB 159 +#define JH7110_SYSCLK_SPDIF_CORE 160 +#define JH7110_SYSCLK_I2STX0_APB 161 +#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 +#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 +#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 +#define JH7110_SYSCLK_I2STX0_BCLK 165 +#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 +#define JH7110_SYSCLK_I2STX0_LRCK 167 +#define JH7110_SYSCLK_I2STX1_APB 168 +#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 +#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 +#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 +#define JH7110_SYSCLK_I2STX1_BCLK 172 +#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 +#define JH7110_SYSCLK_I2STX1_LRCK 174 +#define JH7110_SYSCLK_I2SRX_APB 175 +#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 +#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 +#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 +#define JH7110_SYSCLK_I2SRX_BCLK 179 +#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 +#define JH7110_SYSCLK_I2SRX_LRCK 181 +#define JH7110_SYSCLK_PDM_DMIC 182 +#define JH7110_SYSCLK_PDM_APB 183 +#define JH7110_SYSCLK_TDM_AHB 184 +#define JH7110_SYSCLK_TDM_APB 185 +#define JH7110_SYSCLK_TDM_INTERNAL 186 +#define JH7110_SYSCLK_TDM_TDM 187 +#define JH7110_SYSCLK_TDM_TDM_INV 188 +#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 + +#define JH7110_SYSCLK_END 190 + +/* AONCRG clocks */ +#define JH7110_AONCLK_OSC_DIV4 0 +#define JH7110_AONCLK_APB_FUNC 1 +#define JH7110_AONCLK_GMAC0_AHB 2 +#define JH7110_AONCLK_GMAC0_AXI 3 +#define JH7110_AONCLK_GMAC0_RMII_RTX 4 +#define JH7110_AONCLK_GMAC0_TX 5 +#define JH7110_AONCLK_GMAC0_TX_INV 6 +#define JH7110_AONCLK_GMAC0_RX 7 +#define JH7110_AONCLK_GMAC0_RX_INV 8 +#define JH7110_AONCLK_OTPC_APB 9 +#define JH7110_AONCLK_RTC_APB 10 +#define JH7110_AONCLK_RTC_INTERNAL 11 +#define JH7110_AONCLK_RTC_32K 12 +#define JH7110_AONCLK_RTC_CAL 13 + +#define JH7110_AONCLK_END 14 + +/* STGCRG clocks */ +#define JH7110_STGCLK_HIFI4_CLK_CORE 0 +#define JH7110_STGCLK_USB0_APB 1 +#define JH7110_STGCLK_USB0_UTMI_APB 2 +#define JH7110_STGCLK_USB0_AXI 3 +#define JH7110_STGCLK_USB0_LPM 4 +#define JH7110_STGCLK_USB0_STB 5 +#define JH7110_STGCLK_USB0_APP_125 6 +#define JH7110_STGCLK_USB0_REFCLK 7 +#define JH7110_STGCLK_PCIE0_AXI_MST0 8 +#define JH7110_STGCLK_PCIE0_APB 9 +#define JH7110_STGCLK_PCIE0_TL 10 +#define JH7110_STGCLK_PCIE1_AXI_MST0 11 +#define JH7110_STGCLK_PCIE1_APB 12 +#define JH7110_STGCLK_PCIE1_TL 13 +#define JH7110_STGCLK_PCIE_SLV_MAIN 14 +#define JH7110_STGCLK_SEC_AHB 15 +#define JH7110_STGCLK_SEC_MISC_AHB 16 +#define JH7110_STGCLK_GRP0_MAIN 17 +#define JH7110_STGCLK_GRP0_BUS 18 +#define JH7110_STGCLK_GRP0_STG 19 +#define JH7110_STGCLK_GRP1_MAIN 20 +#define JH7110_STGCLK_GRP1_BUS 21 +#define JH7110_STGCLK_GRP1_STG 22 +#define JH7110_STGCLK_GRP1_HIFI 23 +#define JH7110_STGCLK_E2_RTC 24 +#define JH7110_STGCLK_E2_CORE 25 +#define JH7110_STGCLK_E2_DBG 26 +#define JH7110_STGCLK_DMA1P_AXI 27 +#define JH7110_STGCLK_DMA1P_AHB 28 + +#define JH7110_STGCLK_END 29 + +/* ISPCRG clocks */ +#define JH7110_ISPCLK_DOM4_APB_FUNC 0 +#define JH7110_ISPCLK_MIPI_RX0_PXL 1 +#define JH7110_ISPCLK_DVP_INV 2 +#define JH7110_ISPCLK_M31DPHY_CFG_IN 3 +#define JH7110_ISPCLK_M31DPHY_REF_IN 4 +#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 +#define JH7110_ISPCLK_VIN_APB 6 +#define JH7110_ISPCLK_VIN_SYS 7 +#define JH7110_ISPCLK_VIN_PIXEL_IF0 8 +#define JH7110_ISPCLK_VIN_PIXEL_IF1 9 +#define JH7110_ISPCLK_VIN_PIXEL_IF2 10 +#define JH7110_ISPCLK_VIN_PIXEL_IF3 11 +#define JH7110_ISPCLK_VIN_P_AXI_WR 12 +#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 + +#define JH7110_ISPCLK_END 14 + +/* VOUTCRG clocks */ +#define JH7110_VOUTCLK_APB 0 +#define JH7110_VOUTCLK_DC8200_PIX 1 +#define JH7110_VOUTCLK_DSI_SYS 2 +#define JH7110_VOUTCLK_TX_ESC 3 +#define JH7110_VOUTCLK_DC8200_AXI 4 +#define JH7110_VOUTCLK_DC8200_CORE 5 +#define JH7110_VOUTCLK_DC8200_AHB 6 +#define JH7110_VOUTCLK_DC8200_PIX0 7 +#define JH7110_VOUTCLK_DC8200_PIX1 8 +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 +#define JH7110_VOUTCLK_DSITX_APB 10 +#define JH7110_VOUTCLK_DSITX_SYS 11 +#define JH7110_VOUTCLK_DSITX_DPI 12 +#define JH7110_VOUTCLK_DSITX_TXESC 13 +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 +#define JH7110_VOUTCLK_HDMI_TX_MCLK 15 +#define JH7110_VOUTCLK_HDMI_TX_BCLK 16 +#define JH7110_VOUTCLK_HDMI_TX_SYS 17 + +#define JH7110_VOUTCLK_END 18 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/src/arch/riscv/include/dt-bindings/gpio/gpio.h b/src/arch/riscv/include/dt-bindings/gpio/gpio.h new file mode 100644 index 0000000..b5d5312 --- /dev/null +++ b/src/arch/riscv/include/dt-bindings/gpio/gpio.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * This header provides constants for most GPIO bindings. + * + * Most GPIO bindings include a flags cell as part of the GPIO specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_GPIO_GPIO_H +#define _DT_BINDINGS_GPIO_GPIO_H + +/* Bit 0 express polarity */ +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/* Bit 1 express single-endedness */ +#define GPIO_PUSH_PULL 0 +#define GPIO_SINGLE_ENDED 2 + +/* Bit 2 express Open drain or open source */ +#define GPIO_LINE_OPEN_SOURCE 0 +#define GPIO_LINE_OPEN_DRAIN 4 + +/* + * Open Drain/Collector is the combination of single-ended open drain interface. + * Open Source/Emitter is the combination of single-ended open source interface. + */ +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) + +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 + +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + +/* Bit 6 express pull disable */ +#define GPIO_PULL_DISABLE 64 + +#endif diff --git a/src/arch/riscv/include/dt-bindings/power/starfive,jh7110-pmu.h b/src/arch/riscv/include/dt-bindings/power/starfive,jh7110-pmu.h new file mode 100644 index 0000000..7b4f249 --- /dev/null +++ b/src/arch/riscv/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * Author: Walker Chen walker.chen@starfivetech.com + */ +#ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ +#define __DT_BINDINGS_POWER_JH7110_POWER_H__ + +#define JH7110_PD_SYSTOP 0 +#define JH7110_PD_CPU 1 +#define JH7110_PD_GPUA 2 +#define JH7110_PD_VDEC 3 +#define JH7110_PD_VOUT 4 +#define JH7110_PD_ISP 5 +#define JH7110_PD_VENC 6 + +/* AON Power Domain */ +#define JH7110_AON_PD_DPHY_TX 0 +#define JH7110_AON_PD_DPHY_RX 1 + +#endif diff --git a/src/arch/riscv/include/dt-bindings/reset/starfive,jh7110-crg.h b/src/arch/riscv/include/dt-bindings/reset/starfive,jh7110-crg.h new file mode 100644 index 0000000..eaf4a0d --- /dev/null +++ b/src/arch/riscv/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ + +/* SYSCRG resets */ +#define JH7110_SYSRST_JTAG_APB 0 +#define JH7110_SYSRST_SYSCON_APB 1 +#define JH7110_SYSRST_IOMUX_APB 2 +#define JH7110_SYSRST_BUS 3 +#define JH7110_SYSRST_DEBUG 4 +#define JH7110_SYSRST_CORE0 5 +#define JH7110_SYSRST_CORE1 6 +#define JH7110_SYSRST_CORE2 7 +#define JH7110_SYSRST_CORE3 8 +#define JH7110_SYSRST_CORE4 9 +#define JH7110_SYSRST_CORE0_ST 10 +#define JH7110_SYSRST_CORE1_ST 11 +#define JH7110_SYSRST_CORE2_ST 12 +#define JH7110_SYSRST_CORE3_ST 13 +#define JH7110_SYSRST_CORE4_ST 14 +#define JH7110_SYSRST_TRACE0 15 +#define JH7110_SYSRST_TRACE1 16 +#define JH7110_SYSRST_TRACE2 17 +#define JH7110_SYSRST_TRACE3 18 +#define JH7110_SYSRST_TRACE4 19 +#define JH7110_SYSRST_TRACE_COM 20 +#define JH7110_SYSRST_GPU_APB 21 +#define JH7110_SYSRST_GPU_DOMA 22 +#define JH7110_SYSRST_NOC_BUS_APB 23 +#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +#define JH7110_SYSRST_NOC_BUS_DDRC 29 +#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 + +#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +#define JH7110_SYSRST_AXI_CFG1_AHB 33 +#define JH7110_SYSRST_AXI_CFG1_MAIN 34 +#define JH7110_SYSRST_AXI_CFG0_MAIN 35 +#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36 +#define JH7110_SYSRST_AXI_CFG0_HIFI4 37 +#define JH7110_SYSRST_DDR_AXI 38 +#define JH7110_SYSRST_DDR_OSC 39 +#define JH7110_SYSRST_DDR_APB 40 +#define JH7110_SYSRST_ISP_TOP 41 +#define JH7110_SYSRST_ISP_TOP_AXI 42 +#define JH7110_SYSRST_VOUT_TOP_SRC 43 +#define JH7110_SYSRST_CODAJ12_AXI 44 +#define JH7110_SYSRST_CODAJ12_CORE 45 +#define JH7110_SYSRST_CODAJ12_APB 46 +#define JH7110_SYSRST_WAVE511_AXI 47 +#define JH7110_SYSRST_WAVE511_BPU 48 +#define JH7110_SYSRST_WAVE511_VCE 49 +#define JH7110_SYSRST_WAVE511_APB 50 +#define JH7110_SYSRST_VDEC_JPG 51 +#define JH7110_SYSRST_VDEC_MAIN 52 +#define JH7110_SYSRST_AXIMEM0_AXI 53 +#define JH7110_SYSRST_WAVE420L_AXI 54 +#define JH7110_SYSRST_WAVE420L_BPU 55 +#define JH7110_SYSRST_WAVE420L_VCE 56 +#define JH7110_SYSRST_WAVE420L_APB 57 +#define JH7110_SYSRST_AXIMEM1_AXI 58 +#define JH7110_SYSRST_AXIMEM2_AXI 59 +#define JH7110_SYSRST_INTMEM 60 +#define JH7110_SYSRST_QSPI_AHB 61 +#define JH7110_SYSRST_QSPI_APB 62 +#define JH7110_SYSRST_QSPI_REF 63 + +#define JH7110_SYSRST_SDIO0_AHB 64 +#define JH7110_SYSRST_SDIO1_AHB 65 +#define JH7110_SYSRST_GMAC1_AXI 66 +#define JH7110_SYSRST_GMAC1_AHB 67 +#define JH7110_SYSRST_MAILBOX_APB 68 +#define JH7110_SYSRST_SPI0_APB 69 +#define JH7110_SYSRST_SPI1_APB 70 +#define JH7110_SYSRST_SPI2_APB 71 +#define JH7110_SYSRST_SPI3_APB 72 +#define JH7110_SYSRST_SPI4_APB 73 +#define JH7110_SYSRST_SPI5_APB 74 +#define JH7110_SYSRST_SPI6_APB 75 +#define JH7110_SYSRST_I2C0_APB 76 +#define JH7110_SYSRST_I2C1_APB 77 +#define JH7110_SYSRST_I2C2_APB 78 +#define JH7110_SYSRST_I2C3_APB 79 +#define JH7110_SYSRST_I2C4_APB 80 +#define JH7110_SYSRST_I2C5_APB 81 +#define JH7110_SYSRST_I2C6_APB 82 +#define JH7110_SYSRST_UART0_APB 83 +#define JH7110_SYSRST_UART0_CORE 84 +#define JH7110_SYSRST_UART1_APB 85 +#define JH7110_SYSRST_UART1_CORE 86 +#define JH7110_SYSRST_UART2_APB 87 +#define JH7110_SYSRST_UART2_CORE 88 +#define JH7110_SYSRST_UART3_APB 89 +#define JH7110_SYSRST_UART3_CORE 90 +#define JH7110_SYSRST_UART4_APB 91 +#define JH7110_SYSRST_UART4_CORE 92 +#define JH7110_SYSRST_UART5_APB 93 +#define JH7110_SYSRST_UART5_CORE 94 +#define JH7110_SYSRST_SPDIF_APB 95 + +#define JH7110_SYSRST_PWMDAC_APB 96 +#define JH7110_SYSRST_PDM_DMIC 97 +#define JH7110_SYSRST_PDM_APB 98 +#define JH7110_SYSRST_I2SRX_APB 99 +#define JH7110_SYSRST_I2SRX_BCLK 100 +#define JH7110_SYSRST_I2STX0_APB 101 +#define JH7110_SYSRST_I2STX0_BCLK 102 +#define JH7110_SYSRST_I2STX1_APB 103 +#define JH7110_SYSRST_I2STX1_BCLK 104 +#define JH7110_SYSRST_TDM_AHB 105 +#define JH7110_SYSRST_TDM_CORE 106 +#define JH7110_SYSRST_TDM_APB 107 +#define JH7110_SYSRST_PWM_APB 108 +#define JH7110_SYSRST_WDT_APB 109 +#define JH7110_SYSRST_WDT_CORE 110 +#define JH7110_SYSRST_CAN0_APB 111 +#define JH7110_SYSRST_CAN0_CORE 112 +#define JH7110_SYSRST_CAN0_TIMER 113 +#define JH7110_SYSRST_CAN1_APB 114 +#define JH7110_SYSRST_CAN1_CORE 115 +#define JH7110_SYSRST_CAN1_TIMER 116 +#define JH7110_SYSRST_TIMER_APB 117 +#define JH7110_SYSRST_TIMER0 118 +#define JH7110_SYSRST_TIMER1 119 +#define JH7110_SYSRST_TIMER2 120 +#define JH7110_SYSRST_TIMER3 121 +#define JH7110_SYSRST_INT_CTRL_APB 122 +#define JH7110_SYSRST_TEMP_APB 123 +#define JH7110_SYSRST_TEMP_CORE 124 +#define JH7110_SYSRST_JTAG_CERTIFICATION 125 + +#define JH7110_SYSRST_END 126 + +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + +/* STGCRG resets */ +#define JH7110_STGRST_SYSCON 0 +#define JH7110_STGRST_HIFI4_CORE 1 +#define JH7110_STGRST_HIFI4_AXI 2 +#define JH7110_STGRST_SEC_AHB 3 +#define JH7110_STGRST_E24_CORE 4 +#define JH7110_STGRST_DMA1P_AXI 5 +#define JH7110_STGRST_DMA1P_AHB 6 +#define JH7110_STGRST_USB0_AXI 7 +#define JH7110_STGRST_USB0_APB 8 +#define JH7110_STGRST_USB0_UTMI_APB 9 +#define JH7110_STGRST_USB0_PWRUP 10 +#define JH7110_STGRST_PCIE0_AXI_MST0 11 +#define JH7110_STGRST_PCIE0_AXI_SLV0 12 +#define JH7110_STGRST_PCIE0_AXI_SLV 13 +#define JH7110_STGRST_PCIE0_BRG 14 +#define JH7110_STGRST_PCIE0_CORE 15 +#define JH7110_STGRST_PCIE0_APB 16 +#define JH7110_STGRST_PCIE1_AXI_MST0 17 +#define JH7110_STGRST_PCIE1_AXI_SLV0 18 +#define JH7110_STGRST_PCIE1_AXI_SLV 19 +#define JH7110_STGRST_PCIE1_BRG 20 +#define JH7110_STGRST_PCIE1_CORE 21 +#define JH7110_STGRST_PCIE1_APB 22 + +#define JH7110_STGRST_END 23 + +/* ISPCRG resets */ +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0 +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1 +#define JH7110_ISPRST_M31DPHY_HW 2 +#define JH7110_ISPRST_M31DPHY_B09_AON 3 +#define JH7110_ISPRST_VIN_APB 4 +#define JH7110_ISPRST_VIN_PIXEL_IF0 5 +#define JH7110_ISPRST_VIN_PIXEL_IF1 6 +#define JH7110_ISPRST_VIN_PIXEL_IF2 7 +#define JH7110_ISPRST_VIN_PIXEL_IF3 8 +#define JH7110_ISPRST_VIN_SYS 9 +#define JH7110_ISPRST_VIN_P_AXI_RD 10 +#define JH7110_ISPRST_VIN_P_AXI_WR 11 + +#define JH7110_ISPRST_END 12 + +/* VOUTCRG resets */ +#define JH7110_VOUTRST_DC8200_AXI 0 +#define JH7110_VOUTRST_DC8200_AHB 1 +#define JH7110_VOUTRST_DC8200_CORE 2 +#define JH7110_VOUTRST_DSITX_DPI 3 +#define JH7110_VOUTRST_DSITX_APB 4 +#define JH7110_VOUTRST_DSITX_RXESC 5 +#define JH7110_VOUTRST_DSITX_SYS 6 +#define JH7110_VOUTRST_DSITX_TXBYTEHS 7 +#define JH7110_VOUTRST_DSITX_TXESC 8 +#define JH7110_VOUTRST_HDMI_TX_HDMI 9 +#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10 +#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11 + +#define JH7110_VOUTRST_END 12 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ diff --git a/src/arch/riscv/include/dt-bindings/thermal/thermal.h b/src/arch/riscv/include/dt-bindings/thermal/thermal.h new file mode 100644 index 0000000..bc7babb --- /dev/null +++ b/src/arch/riscv/include/dt-bindings/thermal/thermal.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides constants for most thermal bindings. + * + * Copyright (C) 2013 Texas Instruments + * Eduardo Valentin eduardo.valentin@ti.com + */ + +#ifndef _DT_BINDINGS_THERMAL_THERMAL_H +#define _DT_BINDINGS_THERMAL_THERMAL_H + +/* On cooling devices upper and lower limits */ +#define THERMAL_NO_LIMIT (~0) + +#endif + diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index bddb9ba..166b6a3 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -563,9 +563,24 @@ static int fdt_unflatten_map_entry(const void *blob, uint32_t offset, struct device_tree_reserve_map_entry **new) { - const uint64_t *ptr = (const uint64_t *)(((uint8_t *)blob) + offset); - const uint64_t start = be64toh(ptr[0]); - const uint64_t size = be64toh(ptr[1]); + const uint8_t *ptr = (uint8_t *)blob + offset; + //TODO this currently hits QSPI memory mapped flash on visionfive2 and access that is not natural aligned causes a load access fault exception (not even a misaligned access exception. I guess MMIO misaligned accesss causes load access fault exception instead of misaligned access exception?) TODO visionfive2 also doesn't seem to support unaligned access on non MMIO which is a pain since be32enc and friends all don't support misaligned access and setting up a misaligned access trap handler is terribly slow (and currently not implemented anyway). + const uint64_t start = ((uint64_t)ptr[0] << 56) + | ((uint64_t)ptr[1] << 48) + | ((uint64_t)ptr[2] << 40) + | ((uint64_t)ptr[3] << 32) + | ((uint64_t)ptr[4] << 24) + | ((uint64_t)ptr[5] << 16) + | ((uint64_t)ptr[6] << 8) + | ((uint64_t)ptr[7] << 0); + const uint64_t size = ((uint64_t)ptr[8] << 56) + | ((uint64_t)ptr[9] << 48) + | ((uint64_t)ptr[10] << 40) + | ((uint64_t)ptr[11] << 32) + | ((uint64_t)ptr[12] << 24) + | ((uint64_t)ptr[13] << 16) + | ((uint64_t)ptr[14] << 8) + | ((uint64_t)ptr[15] << 0);
if (!size) return 0; diff --git a/src/mainboard/starfive/Kconfig b/src/mainboard/starfive/Kconfig new file mode 100644 index 0000000..69dbfa5 --- /dev/null +++ b/src/mainboard/starfive/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_STARFIVE + +choice + prompt "Mainboard model" + +source "src/mainboard/starfive/*/Kconfig.name" + +endchoice + +source "src/mainboard/starfive/*/Kconfig" + +config MAINBOARD_VENDOR + default "starfive" + +endif # VENDOR_STARFIVE diff --git a/src/mainboard/starfive/Kconfig.name b/src/mainboard/starfive/Kconfig.name new file mode 100644 index 0000000..3d4c103 --- /dev/null +++ b/src/mainboard/starfive/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_STARFIVE + bool "starfive" diff --git a/src/mainboard/starfive/visionfive2/Kconfig b/src/mainboard/starfive/visionfive2/Kconfig new file mode 100644 index 0000000..0ca681b --- /dev/null +++ b/src/mainboard/starfive/visionfive2/Kconfig @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_STARFIVE_VISIONFIVE2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_STARFIVE_JH7110 + select BOARD_ROMSIZE_KB_16384 + select MISSING_BOARD_RESET + select FLATTENED_DEVICE_TREE + select RISCV_DTS + +config HEAP_SIZE + default 0x40000 # 256 KB + +config MAINBOARD_DIR + default "starfive/visionfive2" + +config MAINBOARD_PART_NUMBER + default "VisionFive2" + +choice + prompt "Choose VISIONFIVE2 model version" + default VISIONFIVE2_V13B + +config VISIONFIVE2_V12A + bool "Visionfive 2 model version V1.2a" +config VISIONFIVE2_V13B + bool "Visionfive 2 model version V1.3b" + +endchoice + +config RISCV_DTS_FILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/dts/visionfive-2-v1.2a.dts" if VISIONFIVE2_V12A + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/dts/visionfive-2-v1.3b.dts" if VISIONFIVE2_V13B + +endif diff --git a/src/mainboard/starfive/visionfive2/Kconfig.name b/src/mainboard/starfive/visionfive2/Kconfig.name new file mode 100644 index 0000000..bc169b7 --- /dev/null +++ b/src/mainboard/starfive/visionfive2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_STARFIVE_VISIONFIVE2 + bool "Visionfive2" diff --git a/src/mainboard/starfive/visionfive2/board_info.txt b/src/mainboard/starfive/visionfive2/board_info.txt new file mode 100644 index 0000000..afecb2d --- /dev/null +++ b/src/mainboard/starfive/visionfive2/board_info.txt @@ -0,0 +1,6 @@ +Category: eval +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Board URL: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html diff --git a/src/mainboard/starfive/visionfive2/bootblock.c b/src/mainboard/starfive/visionfive2/bootblock.c new file mode 100644 index 0000000..a6dbcf0 --- /dev/null +++ b/src/mainboard/starfive/visionfive2/bootblock.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootblock_common.h> +#include <commonlib/bsd/helpers.h> +#include <soc/gpio.h> +#include <soc/jh7110-pinfunc.h> + +struct gpio_config gpio_configs[] = { + // Format: + // { GPIOx, GPEN/DOEN, GPO/DOUT, GPI } + // Basic PINMUX Rules: + // Function | GPO Signal | GPI Signal | GPEN Signal + // ------------------------------------------------------------------ + // Unidirectional input | None | Required | May require + // Unidirectional output | Required | None | May require + // Bidirectional input/output | Required | Required | Required + // + // Not all functions have dedicated GPEN signals. For the input function without a + // GPEN signal, index value should be fixed to 1. + // For the output function without a GPEN signal, the index value should be fixed to 0. + // All functions can be configured to any GPIO (full multiplexing). GPIOs are + // configured by mapping signal indexes to a given GPIO. + // For futher reference see JH7110 TRM (technical reference manual). + + // Configure UART to pins that are routet out as pin headers + // This is the default function, but lets configure it anyway + { 5, 0, GPOUT_SYS_UART0_TX, GPI_NONE }, // UART TX + { 6, 1, 0, GPI_SYS_UART0_RX }, // UART RX + + // Configure JTAG to pins that are routet out as pin headers + { 36, 1, 0, GPI_SYS_JTAG_RST }, + { 61, 1, 0, GPI_SYS_JTAG_TDI }, + { 63, 1, 0, GPI_SYS_JTAG_TMS }, + { 60, 1, 0, GPI_SYS_JTAG_TCK }, + { 44, GPOEN_SYS_JTAG_TDO, GPOUT_SYS_JTAG_TDO, GPI_NONE }, +}; + +void bootblock_mainboard_early_init(void) +{ + for (int i = 0; i < ARRAY_SIZE(gpio_configs); i++) { + gpio_config(gpio_configs[i]); + } +} diff --git a/src/mainboard/starfive/visionfive2/cbfs_spi.c b/src/mainboard/starfive/visionfive2/cbfs_spi.c new file mode 100644 index 0000000..4c9441558 --- /dev/null +++ b/src/mainboard/starfive/visionfive2/cbfs_spi.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot_device.h> +#include <soc/addressmap.h> + +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT(JH7110_QSPI, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/starfive/visionfive2/devicetree.cb b/src/mainboard/starfive/visionfive2/devicetree.cb new file mode 100644 index 0000000..bbca75e --- /dev/null +++ b/src/mainboard/starfive/visionfive2/devicetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/starfive/jh7110 + device cpu_cluster 0 on ops jh7110_cpu_ops end +end diff --git a/src/mainboard/starfive/visionfive2/dts/move-dts.sh b/src/mainboard/starfive/visionfive2/dts/move-dts.sh new file mode 100755 index 0000000..943ab65 --- /dev/null +++ b/src/mainboard/starfive/visionfive2/dts/move-dts.sh @@ -0,0 +1,15 @@ +#!/bin/sh + +linux_path=/home/max/repos/linux-starfive +cb_path=/home/max/coreboot/src/mainboard/starfive/visionfive2/dts/dt-bindings + +# create directories +dirs=$(grep -hroE "dt-bindings/[-a-zA-Z0-9./,.]+" | sed -e "s/^dt-bindings/(.*)/.*/\1/" | sort | uniq) +cd $cb_path +mkdir $(echo $dirs | xargs) +cd - + +# cp files +for f in $(grep -hroE "dt-bindings/[-a-zA-Z0-9./,.]+"); do + cp "$linux_path/include/$f" $cb_path/$(echo $f | sed -e "s/^dt-bindings/(.*)/\1/") +done diff --git a/src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.2a.dts b/src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.2a.dts new file mode 100644 index 0000000..c7a897e --- /dev/null +++ b/src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.2a.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + */ + +/dts-v1/; +#include "visionfive-2.dtsi" + +/ { + model = "StarFive VisionFive 2 v1.2A"; + compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; +}; + +&gmac1 { + phy-mode = "rmii"; + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>, + <&syscrg JH7110_SYSCLK_GMAC1_RX>; + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, + <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + rx-internal-delay-ps = <1900>; + tx-internal-delay-ps = <1350>; +}; diff --git a/src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.3b.dts b/src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.3b.dts new file mode 100644 index 0000000..f1ff09b --- /dev/null +++ b/src/mainboard/starfive/visionfive2/dts/visionfive-2-v1.3b.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + */ + +/dts-v1/; +#include "visionfive-2.dtsi" + +/ { + model = "StarFive VisionFive 2 v1.3B"; + compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; +}; + +&gmac0 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; +}; + +&gmac1 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; +}; + +&phy1 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + rx-internal-delay-ps = <300>; + tx-internal-delay-ps = <0>; +}; + +&mmc1 { + status = "okay"; +}; diff --git a/src/mainboard/starfive/visionfive2/dts/visionfive-2.dtsi b/src/mainboard/starfive/visionfive2/dts/visionfive-2.dtsi new file mode 100644 index 0000000..391c7c6 --- /dev/null +++ b/src/mainboard/starfive/visionfive2/dts/visionfive-2.dtsi @@ -0,0 +1,961 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + */ + +/dts-v1/; +#include <soc/jh7110.dtsi> +#include <soc/jh7110-pinfunc.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c5 = &i2c5; + i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; + pcie0 = &pcie0; + pcie1 = &pcie1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = <4000000>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x2 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + //linux,cma { + // compatible = "shared-dma-pool"; + // reusable; + // size = <0x0 0x20000000>; + // alignment = <0x0 0x1000>; + // alloc-ranges = <0x0 0x70000000 0x0 0x20000000>; + // linux,cma-default; + //}; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; + priority = <224>; + }; + + imx219_clk: imx219-clock { + compatible = "fixed-clock"; + clock-output-names = "imx219_clk"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + imx219_vana_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + imx219_vdig_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdig"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + imx219_vddl_1v2: 1p2v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddl"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + pwmdac_codec: pwmdac-codec { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sound-pwmdac { + compatible = "simple-audio-card"; + simple-audio-card,name = "StarFive-PWMDAC-Sound-Card"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "left_j"; + bitclock-master = <&sndcpu0>; + frame-master = <&sndcpu0>; + + sndcpu0: cpu { + sound-dai = <&pwmdac>; + }; + + codec { + sound-dai = <&pwmdac_codec>; + }; + }; + }; +}; + +&dvp_clk { + clock-frequency = <74250000>; +}; + +&gmac0_rgmii_rxin { + clock-frequency = <125000000>; +}; + +&gmac0_rmii_refin { + clock-frequency = <50000000>; +}; + +&gmac1_rgmii_rxin { + clock-frequency = <125000000>; +}; + +&gmac1_rmii_refin { + clock-frequency = <50000000>; +}; + +&hdmitx0_pixelclk { + clock-frequency = <297000000>; +}; + +&i2srx_bclk_ext { + clock-frequency = <12288000>; +}; + +&i2srx_lrck_ext { + clock-frequency = <192000>; +}; + +&i2stx_bclk_ext { + clock-frequency = <12288000>; +}; + +&i2stx_lrck_ext { + clock-frequency = <192000>; +}; + +&mclk_ext { + clock-frequency = <12288000>; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&rtc_osc { + clock-frequency = <32768>; +}; + +&tdm_ext { + clock-frequency = <49152000>; +}; + +&camss { + assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; + assigned-clock-rates = <49500000>, <198000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + camss_from_csi2rx: endpoint { + remote-endpoint = <&csi2rx_to_camss>; + }; + }; + }; +}; + +&csi2rx { + assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; + assigned-clock-rates = <297000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_from_imx219: endpoint { + remote-endpoint = <&imx219_to_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_to_camss: endpoint { + remote-endpoint = <&camss_from_csi2rx>; + }; + }; + }; +}; + +&dc8200 { + status = "okay"; + + crtc_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + dc_out0: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dc_out_dpi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_enc>; + }; + + }; + + dc_out1: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dc_out_dpi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_enc>; + }; + + }; + }; +}; + +&display { + status = "okay"; + ports = <&crtc_out>; +}; + +&dsi_encoder { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* input */ + enc_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsi_enc:endpoint@0 { + reg = <0>; + remote-endpoint = <&dc_out_dpi1>; + }; + }; + /* output */ + enc_out: port@1 { + reg = <1>; + /*need add a remote-endpoint to dsi bridge*/ + }; + }; +}; + +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <0>; + }; + }; +}; + +&hdmi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_enc: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc_out_dpi0>; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + status = "okay"; + + axp15060: pmic@36 { + compatible = "x-powers,axp15060"; + reg = <0x36>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + + regulators { + vcc_3v3: dcdc1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3"; + }; + + vdd_cpu: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-name = "vdd-cpu"; + }; + + emmc_vdd: aldo4 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "emmc_vdd"; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + status = "okay"; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&imx219_clk>; + reset-gpios = <&sysgpio 18 GPIO_ACTIVE_HIGH>; + VANA-supply = <&imx219_vana_2v8>; + VDIG-supply = <&imx219_vdig_1v8>; + VDDL-supply = <&imx219_vddl_1v2>; + + port { + imx219_to_csi2rx: endpoint { + remote-endpoint = <&csi2rx_from_imx219>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&i2srx { + pinctrl-names = "default"; + pinctrl-0 = <&i2srx_pins>; + status = "okay"; +}; + +&i2stx0 { + pinctrl-names = "default"; + pinctrl-0 = <&mclk_ext_pins>; + status = "okay"; +}; + +&i2stx1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2stx1_pins>; + status = "okay"; +}; + +&mmc0 { + max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + assigned-clock-rates = <50000000>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + cap-mmc-hw-reset; + post-power-on-delay-ms = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; + status = "okay"; +}; + +&mmc1 { + max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + assigned-clock-rates = <50000000>; + bus-width = <4>; + no-sdio; + no-mmc; + broken-cd; + cap-sd-highspeed; + post-power-on-delay-ms = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; +}; + +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&pwmdac { + pinctrl-names = "default"; + pinctrl-0 = <&pwmdac_pins>; + status = "okay"; +}; + +&qspi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x80000>; + }; + uboot-env@f0000 { + reg = <0xf0000 0x10000>; + }; + uboot@100000 { + reg = <0x100000 0x400000>; + }; + reserved-data@600000 { + reg = <0x600000 0xa00000>; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&sysgpio { + hdmi_pins: hdmi-0 { + hdmi-cec-pins { + pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA, + GPOEN_SYS_HDMI_CEC_SDA, + GPI_SYS_HDMI_CEC_SDA)>; + input-enable; + bias-pull-up; + }; + + hdmi-hpd-pins { + pinmux = <GPIOMUX(15, GPOUT_HIGH, + GPOEN_ENABLE, + GPI_SYS_HDMI_HPD)>; + input-enable; + bias-disable; /* external pull-up */ + }; + + hdmi-scl-pins { + pinmux = <GPIOMUX(0, GPOUT_SYS_HDMI_DDC_SCL, + GPOEN_SYS_HDMI_DDC_SCL, + GPI_SYS_HDMI_DDC_SCL)>; + input-enable; + bias-pull-up; + }; + + hdmi-sda-pins { + pinmux = <GPIOMUX(1, GPOUT_SYS_HDMI_DDC_SDA, + GPOEN_SYS_HDMI_DDC_SDA, + GPI_SYS_HDMI_DDC_SDA)>; + input-enable; + bias-pull-up; + }; + }; + + i2c0_pins: i2c0-0 { + i2c-pins { + pinmux = <GPIOMUX(57, GPOUT_LOW, + GPOEN_SYS_I2C0_CLK, + GPI_SYS_I2C0_CLK)>, + <GPIOMUX(58, GPOUT_LOW, + GPOEN_SYS_I2C0_DATA, + GPI_SYS_I2C0_DATA)>; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c2_pins: i2c2-0 { + i2c-pins { + pinmux = <GPIOMUX(3, GPOUT_LOW, + GPOEN_SYS_I2C2_CLK, + GPI_SYS_I2C2_CLK)>, + <GPIOMUX(2, GPOUT_LOW, + GPOEN_SYS_I2C2_DATA, + GPI_SYS_I2C2_DATA)>; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c5_pins: i2c5-0 { + i2c-pins { + pinmux = <GPIOMUX(19, GPOUT_LOW, + GPOEN_SYS_I2C5_CLK, + GPI_SYS_I2C5_CLK)>, + <GPIOMUX(20, GPOUT_LOW, + GPOEN_SYS_I2C5_DATA, + GPI_SYS_I2C5_DATA)>; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c6_pins: i2c6-0 { + i2c-pins { + pinmux = <GPIOMUX(16, GPOUT_LOW, + GPOEN_SYS_I2C6_CLK, + GPI_SYS_I2C6_CLK)>, + <GPIOMUX(17, GPOUT_LOW, + GPOEN_SYS_I2C6_DATA, + GPI_SYS_I2C6_DATA)>; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2srx_pins: i2srx-0 { + clk-sd-pins { + pinmux = <GPIOMUX(38, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_BCLK)>, + <GPIOMUX(63, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_LRCK)>, + <GPIOMUX(38, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2STX1_BCLK)>, + <GPIOMUX(63, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2STX1_LRCK)>, + <GPIOMUX(61, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_SDIN0)>; + input-enable; + }; + }; + + i2stx1_pins: i2stx1-0 { + sd-pins { + pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + input-disable; + }; + }; + + mclk_ext_pins: mclk-ext-0 { + mclk-ext-pins { + pinmux = <GPIOMUX(4, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_MCLK_EXT)>; + input-enable; + }; + }; + + mmc0_pins: mmc0-0 { + rst-pins { + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mmc-pins { + pinmux = <PINMUX(64, 0)>, + <PINMUX(65, 0)>, + <PINMUX(66, 0)>, + <PINMUX(67, 0)>, + <PINMUX(68, 0)>, + <PINMUX(69, 0)>, + <PINMUX(70, 0)>, + <PINMUX(71, 0)>, + <PINMUX(72, 0)>, + <PINMUX(73, 0)>; + bias-pull-up; + drive-strength = <12>; + input-enable; + }; + }; + + mmc1_pins: mmc1-0 { + clk-pins { + pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mmc-pins { + pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, + GPOEN_SYS_SDIO1_CMD, + GPI_SYS_SDIO1_CMD)>, + <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, + GPOEN_SYS_SDIO1_DATA0, + GPI_SYS_SDIO1_DATA0)>, + <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, + GPOEN_SYS_SDIO1_DATA1, + GPI_SYS_SDIO1_DATA1)>, + <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, + GPOEN_SYS_SDIO1_DATA2, + GPI_SYS_SDIO1_DATA2)>, + <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, + GPOEN_SYS_SDIO1_DATA3, + GPI_SYS_SDIO1_DATA3)>; + bias-pull-up; + drive-strength = <12>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + pcie0_pins: pcie0-0 { + clkreq-pins { + pinmux = <GPIOMUX(27, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(32, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = <GPIOMUX(29, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(21, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pwm_pins: pwm-0 { + pwm-pins { + pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0, + GPOEN_SYS_PWM0_CHANNEL0, + GPI_NONE)>, + <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1, + GPOEN_SYS_PWM0_CHANNEL1, + GPI_NONE)>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pwmdac_pins: pwmdac-0 { + pwmdac-pins { + pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, + GPOEN_ENABLE, + GPI_NONE)>, + <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + drive-strength = <2>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + spi0_pins: spi0-0 { + mosi-pins { + pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + miso-pins { + pinmux = <GPIOMUX(53, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_SPI0_RXD)>; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + + sck-pins { + pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK, + GPOEN_ENABLE, + GPI_SYS_SPI0_CLK)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + ss-pins { + pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, + GPOEN_ENABLE, + GPI_SYS_SPI0_FSS)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + + tdm_pins: tdm-0 { + tx-pins { + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = <GPIOMUX(61, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_RXD)>; + input-enable; + }; + + sync-pins { + pinmux = <GPIOMUX(63, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_SYNC)>; + input-enable; + }; + + pcmclk-pins { + pinmux = <GPIOMUX(38, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_CLK)>; + input-enable; + }; + }; + + uart0_pins: uart0-0 { + tx-pins { + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = <GPIOMUX(6, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_UART0_RX)>; + bias-disable; /* external pull-up */ + drive-strength = <2>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; + +&tdm { + pinctrl-names = "default"; + pinctrl-0 = <&tdm_pins>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&U74_1 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply = <&vdd_cpu>; +}; diff --git a/src/mainboard/starfive/visionfive2/fixup_fdt.c b/src/mainboard/starfive/visionfive2/fixup_fdt.c new file mode 100644 index 0000000..45dc316 --- /dev/null +++ b/src/mainboard/starfive/visionfive2/fixup_fdt.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include <soc/sdram.h> +#include <cbfs.h> +#include <device_tree.h> +#include <bootstate.h> +#include <mcall.h> + +//static void fixup_memory(struct device_tree_node *parent) +//{ +// struct device_tree_node *node; +// list_for_each(node, parent->children, list_node) { +// if (!strcmp("memory@80000000", node->name)) { +// struct device_tree_prop *prop; +// list_for_each(prop, parent->properties, list_node) { +// if (!strcmp("device_type", prop->prop.name) +// && !strcmp("memory", (char *)prop->prop.data)) { +// u64 addrs[1], sizes[1]; +// addrs[0] = JH7110_DRAM; +// sizes[0] = sdram_size(); +// dt_add_reg_prop(node, addrs, sizes, 1, 2, 2); +// break; +// } +// } +// break; +// } +// } +//} + +static void fixup_fdt(void *unused) +{ + printk(BIOS_DEBUG, "Fix up FDT\n"); + + void *fdt_rom = cbfs_map("FDT", NULL); + if (fdt_rom == NULL) { + printk(BIOS_ERR, "Unable to load FDT from CBFS\n"); + return; + } + + struct device_tree *tree = fdt_unflatten(fdt_rom); + if (!tree) { + printk(BIOS_ERR, "Failed to flatten devicetree\n"); + return; + } + //fixup_memory(tree->root); + + //void *dt = cbmem_add(CBMEM_ID_FDT, dt_flat_size(tree)); + void *dt = malloc(dt_flat_size(tree)); + if (dt == NULL) { + printk(BIOS_ERR, "Unable to allocate memory for flat device tree\n"); + return; + } + dt_flatten(tree, dt); + + printk(BIOS_DEBUG, "Loaded FDT at: %p\n", dt); + + for (int i = 0; i < CONFIG_MAX_CPUS; i++) + OTHER_HLS(i)->fdt = dt; +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, fixup_fdt, NULL); diff --git a/src/mainboard/starfive/visionfive2/mainboard.c b/src/mainboard/starfive/visionfive2/mainboard.c new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starfive/visionfive2/mainboard.c @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starfive/visionfive2/romstage.c b/src/mainboard/starfive/visionfive2/romstage.c new file mode 100644 index 0000000..fae13bb --- /dev/null +++ b/src/mainboard/starfive/visionfive2/romstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/encoding.h> +#include <cbmem.h> +#include <console/console.h> +#include <program_loading.h> +#include <romstage_common.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/sdram.h> +#include <endian.h> +#include <device/mmio.h> +#include <bootblock_common.h> +#include <halt.h> +#include <console/console.h> +#include <lib.h> +#include <commonlib/bsd/helpers.h> +#include <delay.h> +#include <arch/pmp.h> + +void __noreturn romstage_main(void) +{ + clock_init(); + + sdram_init((u64)8*GiB); //TODO there is also a 4 GiB version of visionfive2 + + // Test QSPI + hexdump((void *)JH7110_QSPI, 2); + + setup_pmp(JH7110_DRAM, sdram_size(), PMP_R | PMP_W | PMP_X); + + cbmem_initialize_empty(); + + run_ramstage(); +} diff --git a/src/soc/starfive/jh7110/Kconfig b/src/soc/starfive/jh7110/Kconfig new file mode 100644 index 0000000..b67a42a --- /dev/null +++ b/src/soc/starfive/jh7110/Kconfig @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SOC_STARFIVE_JH7110 + bool + select ARCH_RISCV_RV64 + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP + select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select RISCV_USE_ARCH_TIMER + select UART_OVERRIDE_REFCLK + select RISCV_HAS_OPENSBI + +config SEPARATE_ROMSTAGE + default n if SOC_STARFIVE_JH7110 + +if SOC_STARFIVE_JH7110 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/starfive/jh7110/memlayout.ld" + +config RISCV_ARCH + string + default "rv64imac" + +config RISCV_ABI + string + default "lp64" + +config RISCV_CODEMODEL + string + default "medany" + +# 4x U74 cores (RV64IMAFDC) + 1x S7 core (RV64IMAC) +config MAX_CPUS + int + default 5 + +config RISCV_WORKING_HARTID + int + default 1 # use U7 core as S7 core does not support supervisor mode + +config OPENSBI_PLATFORM + string + default "generic" + +config OPENSBI_TEXT_START + hex + default 0x40000000 + +config OPENSBI_FW_DYNAMIC_BOOT_HART + int + default 1 + help + Choose the first U74 core as boot hart since + hart 0 is the S7 which does not support Supervisor mode + +endif diff --git a/src/soc/starfive/jh7110/bootblock.c b/src/soc/starfive/jh7110/bootblock.c new file mode 100644 index 0000000..d0736ee --- /dev/null +++ b/src/soc/starfive/jh7110/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/encoding.h> +#include <bootblock_common.h> + +void bootblock_soc_early_init(void) +{ + write_csr(0x7c1, 0); // CSR_U74_FEATURE_DISABLE (enable all Features) +} diff --git a/src/soc/starfive/jh7110/cbmem.c b/src/soc/starfive/jh7110/cbmem.c new file mode 100644 index 0000000..a3e369b --- /dev/null +++ b/src/soc/starfive/jh7110/cbmem.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <soc/addressmap.h> +#include <soc/sdram.h> + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)JH7110_DRAM + sdram_size(); +} diff --git a/src/soc/starfive/jh7110/chip.c b/src/soc/starfive/jh7110/chip.c new file mode 100644 index 0000000..f4c9a11 --- /dev/null +++ b/src/soc/starfive/jh7110/chip.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <device/device.h> +#include <soc/addressmap.h> +#include <symbols.h> + +static void jh7110_read_resources(struct device *dev) +{ + int index = 0; + ram_from_to(dev, index++, JH7110_DRAM, (uintptr_t)cbmem_top()); +} + +struct device_operations jh7110_cpu_ops = { + .read_resources = jh7110_read_resources, +}; + +struct chip_operations soc_starfive_jh7110_ops = { + .name = "STARFIVE JH7110", +}; diff --git a/src/soc/starfive/jh7110/clint.c b/src/soc/starfive/jh7110/clint.c new file mode 100644 index 0000000..a19c207 --- /dev/null +++ b/src/soc/starfive/jh7110/clint.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mcall.h> +#include <stdint.h> +#include <device/mmio.h> +#include <soc/addressmap.h> + +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIMECMP 0x4000 + +void mtime_init(void) +{ + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)(JH7110_CLINT + CLINT_MTIME); + HLS()->timecmp = (uint64_t *)(JH7110_CLINT + CLINT_MTIMECMP + 8 * hart_id); +} + +void set_msip(int hartid, int val) +{ + write32((void *)(JH7110_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/starfive/jh7110/clock_reset.c b/src/soc/starfive/jh7110/clock_reset.c new file mode 100644 index 0000000..695c39c --- /dev/null +++ b/src/soc/starfive/jh7110/clock_reset.c @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong yanhong.wang@starfivetech.com + * + * The GMAC0 and GMAC1 settings have been copied from starfives u-boot fork + */ + +// This file is used for setting up clocks and get devices out of reset + +#include <device/mmio.h> +#include <stdint.h> +#include <soc/addressmap.h> +#include <delay.h> +#include <soc/clock.h> +#include <halt.h> + +#define AON_IOMUX_CFG JH7110_AON_GPIO // AON (Always on) multiplexing configuration +#define SYS_IOMUX_CFG JH7110_SYS_IOMUX + +// =============================================== +// SYS CRG registers +// =============================================== + +#define CLK_MUX_SHIFT 24 +#define CLK_MUX_MASK (0x3F << CLK_MUX_SHIFT) //TODO use GENMASK + +#define CLK_ENABLE_SHIFT 31 +#define CLK_ENABLE_MASK (1 << CLK_ENABLE_SHIFT) + +#define CLK_DIV_MASK GENMASK(23, 0) + +// clock enable, divisor and multiplexer register + +#define CLK_CPU_ROOT_OFFSET JH7110_SYS_CRG(0x0) +# define CLK_CPU_ROOT_OSC 0 +# define CLK_CPU_ROOT_PLL0 1 + +#define CLK_CPU_CORE_OFFSET JH7110_SYS_CRG(0x4) + +#define CLK_CPU_BUS_OFFSET JH7110_SYS_CRG(0x8) + +#define CLK_GPU_ROOT_OFFSET JH7110_SYS_CRG(0xc) +# define CLK_GPU_ROOT_PLL2 0 +# define CLK_GPU_ROOT_PLL1 1 + +#define CLK_PERIPHERAL_ROOT_OFFSET JH7110_SYS_CRG(0x10) +# define CLK_PERIPHERAL_ROOT_PLL0 0 +# define CLK_PERIPHERAL_ROOT_PLL2 1 + +#define CLK_BUS_ROOT_OFFSET JH7110_SYS_CRG(0x14) +# define CLK_BUS_ROOT_OSC 0 +# define CLK_BUS_ROOT_PLL2 1 + +#define CLK_PERH_ROOT_OFFSET JH7110_SYS_CRG(0x14) +# define CLK_PERH_ROOT_MASK CLK_MUX_MASK + +#define CLK_DDR_BUS JH7110_SYS_CRG(0xac) +#define CLK_DDR_BUS_MASK CLK_MUX_MASK +# define CLK_DDR_BUS_OSC_DIV2 0 +# define CLK_DDR_BUS_PLL1_DIV2 1 +# define CLK_DDR_BUS_PLL1_DIV4 2 +# define CLK_DDR_BUS_PLL1_DIV8 3 + +#define CLK_STG_MTRX_GROUP_0_MAIN_OFFSET JH7110_SYS_CRG(0x44) +#define CLK_STG_MTRX_GROUP_0_BUS_OFFSET JH7110_SYS_CRG(0x48) +#define CLK_STG_MTRX_GROUP_0_STG_OFFSET JH7110_SYS_CRG(0x4c) +#define CLK_STG_MTRX_GROUP_1_MAIN_OFFSET JH7110_SYS_CRG(0x50) +#define CLK_STG_MTRX_GROUP_1_BUS_OFFSET JH7110_SYS_CRG(0x54) +#define CLK_STG_MTRX_GROUP_1_STG_OFFSET JH7110_SYS_CRG(0x58) +#define CLK_STG_MTRX_GROUP_1_HIFI_OFFSET JH7110_SYS_CRG(0x5c) +#define CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI JH7110_SYS_CRG(0x9c) + +#define CLK_QSPI_OFFSET JH7110_SYS_CRG(0x168) +# define CLK_QSPI_OSC 0 +# define CLK_QSPI_QSPI_REF_SRC 1 + +#define CLK_NOC_STG_AXI_OFFSET JH7110_SYS_CRG(0x180) +#define CLK_TIMER_APB_OFFSET JH7110_SYS_CRG(0x1F0) +#define CLK_TIMER_0_OFFSET JH7110_SYS_CRG(0x1F4) +#define CLK_TIMER_1_OFFSET JH7110_SYS_CRG(0x1F8) +#define CLK_TIMER_2_OFFSET JH7110_SYS_CRG(0x1FC) +#define CLK_TIMER_3_OFFSET JH7110_SYS_CRG(0x200) +#define CLK_UART0_APB_OFFSET JH7110_SYS_CRG(0x244) +#define CLK_UART0_CORE_OFFSET JH7110_SYS_CRG(0x248) + +// reset asser/deassert register + +#define SOFTWARE_RESET_3_OFFSET JH7110_SYS_CRG(0x304) +#define RESET_STATUS_3_OFFSET JH7110_SYS_CRG(0x314) +# define SI5_TIMER_RSTN_APB_SHIFT 21 +# define SI5_TIMER_RSTN_TIMER0_SHIFT 22 +# define SI5_TIMER_RSTN_TIMER1_SHIFT 23 +# define SI5_TIMER_RSTN_TIMER2_SHIFT 24 +# define SI5_TIMER_RSTN_TIMER3_SHIFT 25 + +// reset status registers + +#define SYS_CRG_RESET0 JH7110_SYS_CRG(0x308) +# define RSTN_U0_DDR_SFT7110_RSTN_AXI_SHIFT 6 // Advanced Extensible Interface +# define RSTN_U0_DDR_SFT7110_RSTN_OSC_SHIFT 7 +# define RSTN_U0_DDR_SFT7110_RSTN_APB_SHIFT 8 // Advanced Peripheral Bus +#define SYS_CRG_RESET1 JH7110_SYS_CRG(0x30c) +#define SYS_CRG_RESET2 JH7110_SYS_CRG(0x310) +#define SYS_CRG_RESET3 JH7110_SYS_CRG(0x314) + +// =============================================== +// AON CRG (Always ON configuration register) +// =============================================== + +#define CLK_AON_APB_OFFSET JH7110_AON_CRG(0x4) +# define CLK_AON_APB_OSC_DIV4 0 +# define CLK_AON_APB_OSC 1 + +// =============================================== +// PLL (Phased Locked Loop) +// =============================================== + + +#define PLL0_PD_OFFSET JH7110_SYS_SYSCONSAIF_SYSCFG(32) //TODO from TRM and u-boot (according to Linux its 0x18) +#define PLL0_PD_MASK BIT(27) +#define PLL0_DACPD_MASK BIT(24) +#define PLL0_DSMPD_MASK BIT(25) +#define PLL0_FBDIV_SHIFT 0 +#define PLL0_FBDIV_MASK GENMASK(11, 0) +#define PLL0_PREDIV_SHIFT 0 +#define PLL0_PREDIV_MASK GENMASK(5, 0) +#define PLL0_POSTDIV1_SHIFT 28 +#define PLL0_POSTDIV1_MASK GENMASK(29, 28) + +#define PLL1_PD_MASK BIT(27) +#define PLL1_DACPD_MASK BIT(15) +#define PLL1_DSMPD_MASK BIT(16) +#define PLL1_FBDIV_SHIFT 17 +#define PLL1_FBDIV_MASK GENMASK(28, 17) +#define PLL1_PREDIV_SHIFT 0 +#define PLL1_PREDIV_MASK GENMASK(5, 0) +#define PLL1_POSTDIV1_MASK GENMASK(29, 28) + +#define PLL2_PD_MASK BIT(27) +#define PLL2_DACPD_MASK BIT(15) +#define PLL2_DSMPD_MASK BIT(16) +#define PLL2_FBDIV_SHIFT 17 +#define PLL2_FBDIV_MASK GENMASK(28, 17) +#define PLL2_PREDIV_SHIFT 0 +#define PLL2_PREDIV_MASK GENMASK(5, 0) +#define PLL2_POSTDIV1_MASK GENMASK(29, 28) + +#define PLL_PD_OFF 1 +#define PLL_PD_ON 0 + +// =============== +// other +// =============== + + +// source clock for all 3 system PLLs from external oszilator +#define REFCLK (24*1000*1000) + +struct jh7110_pll { + //u64 rate; // output frequency in Hz (= REFCLK / prediv * fbdiv) + u32 prediv; // PLL pre divider (dividing REFCLK) + u32 fbdiv; // PLL integer feedback divider + u32 frac; // PLL fractional feedback divider (only used in Fraction Multiple Mode) + //u32 postdiv1; // PLL post divider 1 + //u32 postdiv2; // PLL post divider 2 +}; + +static const struct jh7110_pll jh7110_pll0_tbl[] = { + { .prediv = 8, .fbdiv = 125 }, // 375000000 Hz = 375 MHz + { .prediv = 6, .fbdiv = 125 }, // 500000000 Hz = 500 MHz + { .prediv = 24, .fbdiv = 625 }, // 625000000 Hz = 625 MHz + { .prediv = 4, .fbdiv = 125 }, // 750000000 Hz = 750 MHz + { .prediv = 24, .fbdiv = 875 }, // 875000000 Hz = 875 MHz + { .prediv = 3, .fbdiv = 125 }, // 1000000000 Hz = 1000 MHz + { .prediv = 12, .fbdiv = 625 }, // 1250000000 Hz = 1250 MHz + { .prediv = 24, .fbdiv = 1375 }, // 1375000000 Hz = 1375 MHz + { .prediv = 2, .fbdiv = 125 }, // 1500000000 Hz = 1500 MHz + { .prediv = 24, .fbdiv = 1625 }, // 1625000000 Hz = 1625 MHz + { .prediv = 12, .fbdiv = 875 }, // 1750000000 Hz = 1750 MHz + { .prediv = 3, .fbdiv = 225 }, // 1800000000 Hz = 1800 MHz +}; + +static const struct jh7110_pll jh7110_pll1_tbl[] = { + { .prediv = 12, .fbdiv = 533 }, // 1066000000 Hz = 1066 MHz + { .prediv = 1, .fbdiv = 50 }, // 1200000000 Hz = 1200 MHz + { .prediv = 6, .fbdiv = 350 }, // 1400000000 Hz = 1400 MHz + { .prediv = 3, .fbdiv = 200 }, // 1600000000 Hz = 1600 MHz +}; + +static const struct jh7110_pll jh7110_pll2_tbl[] = { + { .prediv = 2, .fbdiv = 99 }, // 1188000000 Hz = 1188 MHz + { .prediv = 15, .fbdiv = 768 }, // 1228800000 Hz = 1228.8 MHz +}; + +static void clk_set_mux(uint32_t reg, int mux) +{ + clrsetbits32p(reg, CLK_MUX_MASK, (mux << CLK_MUX_SHIFT)); +} + +static void clk_set_div(uint32_t reg, int div) +{ + clrsetbits32p(reg, CLK_DIV_MASK, div); +} + +static void clk_enable(uint32_t reg) +{ + clrsetbits32p(reg, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); +} + +static void jh7110_pll2_set_rate(struct jh7110_pll pll) +{ + //// Before changing PLL2 set GPU (clk_gpu_root) to use PLL1 instead of PLL2 + //clrsetbits32p(CLK_GPU_ROOT_OFFSET, CLK_GPU_ROOT_MASK, 0); + + //// Before changing PLL2 set clk_bus_root to use 24MHz Oscilator instead of PLL2 + //clrsetbits32p(CLK_BUS_ROOT_OFFSET, CLK_BUS_ROOT_MASK, 0); + + //// Before changing PLL2 set clk_perh_root (peripheral clock) to use PLL0 instead of PLL2 + //clrsetbits32p(CLK_PERH_ROOT_OFFSET, CLK_PERH_ROOT_MASK, 0); + + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(48), PLL2_PD_MASK, PLL_PD_OFF); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL2_DACPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL2_DSMPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL2_FBDIV_MASK, (pll.fbdiv << PLL2_FBDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(48), PLL2_POSTDIV1_MASK, 0); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(52), PLL2_PREDIV_MASK, (pll.prediv << PLL2_PREDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(48), PLL2_PD_MASK, PLL_PD_ON); + + //// Set clk_perh_root to use PLL2 again + //clrsetbits32p(CLK_PERH_ROOT_OFFSET, CLK_PERH_ROOT_MASK, (1 << CLK_PERH_ROOT_SHIFT)); + + //// Set clk_bus_root to use PLL2 again + //clrsetbits32p(CLK_BUS_ROOT_OFFSET, CLK_BUS_ROOT_MASK, (1 << CLK_BUS_ROOT_SHIFT)); + + //// Set GPU to use PLL2 again + //clrsetbits32p(CLK_GPU_ROOT_OFFSET, CLK_GPU_ROOT_MASK, (1 << CLK_GPU_ROOT_SHIFT)); +} + +static void jh7110_pll1_set_rate(struct jh7110_pll pll) +{ + // switch DDR clock to external oszillator before configuring PLL1 + clk_set_mux(CLK_DDR_BUS, CLK_DDR_BUS_OSC_DIV2); + + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(40), PLL1_PD_MASK, PLL_PD_OFF); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_DACPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_DSMPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_FBDIV_MASK, (pll.fbdiv << PLL1_FBDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(40), PLL1_POSTDIV1_MASK, 0); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL1_PREDIV_MASK, (pll.prediv << PLL1_PREDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_PD_MASK, PLL_PD_ON); + + // wait before switching DDR clock back to PLL1 + udelay(100); //TODO check timing + clk_set_mux(CLK_DDR_BUS, CLK_DDR_BUS_PLL1_DIV2); +} + +static void jh7110_pll0_set_rate(struct jh7110_pll pll) +{ + // Before changing PLL0 set CPU to use the 24MHz Oscilator instead of PLL0 + clk_set_mux(CLK_CPU_ROOT_OFFSET, CLK_CPU_ROOT_OSC); + + // values on reset (tested): fbdiv: 83, prediv: 1, postdiv: 1 + //uint32_t fbdiv = read32p(JH7110_SYS_SYSCONSAIF_SYSCFG(28)) & JH7110_PLL0_FBDIV_MASK; + //uint32_t prediv = read32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36)) & JH7110_PLL0_PREDIV_MASK; + //uint32_t postdiv = (read32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32)) & JH7110_PLL0_POSTDIV1_MASK) >> JH7110_PLL0_POSTDIV1_SHIFT; + //die("fbdiv: %d, prediv: %d, postdiv: %d\n", fbdiv, prediv, postdiv); + + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32), PLL0_PD_MASK, PLL_PD_OFF); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(24), PLL0_DACPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(24), PLL0_DSMPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(28), PLL0_FBDIV_MASK, pll.fbdiv << PLL0_FBDIV_SHIFT); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32), PLL0_POSTDIV1_MASK, 1 << PLL0_POSTDIV1_SHIFT); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL0_PREDIV_MASK, pll.prediv << PLL0_PREDIV_SHIFT); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32), PLL0_PD_MASK, PLL_PD_ON); + + // Set CPU clock divider to 1 + clk_set_div(CLK_CPU_CORE_OFFSET, 1); + // Set CPU to use PLL0 + clk_set_mux(CLK_CPU_ROOT_OFFSET, CLK_CPU_ROOT_PLL0); +} + +static void clock_pll_init(void) +{ + jh7110_pll0_set_rate(jh7110_pll0_tbl[5]); // 1000 MHz + jh7110_pll1_set_rate(jh7110_pll1_tbl[0]); // 1066 MHz + jh7110_pll2_set_rate(jh7110_pll2_tbl[1]); // 1188 MHz +} + +// enable STG MTRX clocks (TODO what is STG_MTRX?) +static void clk_stg_mtrx(void) +{ + clrsetbits32p(CLK_STG_MTRX_GROUP_0_MAIN_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_0_BUS_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_0_STG_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + + clrsetbits32p(CLK_STG_MTRX_GROUP_1_MAIN_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_1_BUS_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_1_STG_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_1_HIFI_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); +} + +static void clk_cpu_root(void) +{ + // init cpu clock + clk_set_mux(CLK_CPU_ROOT_OFFSET, CLK_CPU_ROOT_PLL0); + clk_set_div(CLK_CPU_CORE_OFFSET, 1); + clk_set_div(CLK_CPU_BUS_OFFSET, 2); + + clk_stg_mtrx(); +} + +static void clk_ddr_root(void) +{ +} + +static void clk_gpu_root(void) +{ + clk_set_mux(CLK_GPU_ROOT_OFFSET, CLK_GPU_ROOT_PLL2); +} + +static void clk_bus_root(void) +{ + clk_set_mux(CLK_BUS_ROOT_OFFSET, CLK_BUS_ROOT_PLL2); + + // enable clk_axi_cfg0 (not sure if that is the correct register) + clk_enable(CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI); +} + +static void clk_perh_root(void) +{ + clk_set_mux(CLK_PERIPHERAL_ROOT_OFFSET, CLK_PERIPHERAL_ROOT_PLL2); + + // not really sure if these are part of the peripheral root. + // it is also not clear where they belong in the clock structure of the TRM + clk_enable(CLK_NOC_STG_AXI_OFFSET); + clk_set_mux(CLK_AON_APB_OFFSET, CLK_AON_APB_OSC); + clk_set_mux(CLK_QSPI_OFFSET, CLK_QSPI_QSPI_REF_SRC); + //clk_set_div(CLK_QSPI_OFFSET, 10); TODO try smaller divider for faster QSPI access + clk_enable(CLK_QSPI_OFFSET); +} + +void clock_init(void) +{ + // CPU freq: 1250MHz (should be current) + // DDR clk: 2133M (8GB) + // idcode: 0x1860C8 + + clock_pll_init(); + + // the names of the functions are references to the clock structure figure in the TRM + + clk_cpu_root(); + + clk_ddr_root(); + // put DDR into reset + setbits32p(SYS_CRG_RESET1, (1 << RSTN_U0_DDR_SFT7110_RSTN_AXI_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_OSC_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_APB_SHIFT)); + + // get DDR out of reset + clrbits32p(SYS_CRG_RESET1, (1 << RSTN_U0_DDR_SFT7110_RSTN_AXI_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_OSC_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_APB_SHIFT)); + + clk_gpu_root(); + + clk_bus_root(); + + //clk_venc_root(); + + //clk_vdec_root(); + + //clk_gmacusb_root(); + + //clk_audio_root(); + + clk_perh_root(); + + //clk_isp_root(); + + //clk_vout_root(); + + // set GPIO to 3.3V + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(12), 0xF, 0x0); + + // Improved GMAC0 TX I/O PAD capability + clrsetbits32p(AON_IOMUX_CFG + 0x78, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x7c, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x80, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x84, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x88, 0x3, BIT(0) & 0x3); + + // Improved GMAC1 TX I/O PAD capability + clrsetbits32p(SYS_IOMUX_CFG + 0x26c, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x270, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x274, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x278, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x27c, 0x3, BIT(0) & 0x3); + + // enable UART clock + clrsetbits32p(CLK_UART0_APB_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_UART0_CORE_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + + // TODO timer_init(); + // enable clocks for timer + clrsetbits32p(CLK_TIMER_APB_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_0_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_1_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_2_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_3_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + + // pull timer out of reset + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_APB_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER0_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER1_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER2_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER3_SHIFT); +} diff --git a/src/soc/starfive/jh7110/gpio.c b/src/soc/starfive/jh7110/gpio.c new file mode 100644 index 0000000..1a56286 --- /dev/null +++ b/src/soc/starfive/jh7110/gpio.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/jh7110-pinfunc.h> +#include <stdint.h> +#include <arch/mmio.h> +#include <delay.h> +#include <assert.h> +#include <device/mmio.h> + +// SYS IOMUX CFG +#define SYS_IOMUX_CFG JH7110_SYS_IOMUX +// SYS IOMUX CFGSAIF FMUX +#define SYS_IOMUX_CFGSAIF_FMUX(x) (SYS_IOMUX_CFG + x * 4) +// SYS IOMUX CFGSAIF SYSCFG IOIRQ +#define SYS_IOMUX_CFGSAIF_SYSCFG_IOIRQ(x) (SYS_IOMUX_CFG + x * 4) +// SYS IOMUX CFGSAIF SYSCFG +#define SYS_IOMUX_CFGSAIF_SYSCFG(x) (SYS_IOMUX_CFG + x) + +#define NR_GPIOS 64 + +#define GPIO_DOEN 0x0 +#define GPIO_DOUT 0x40 +#define GPIO_GPI 0x80 +#define GPIO_GPIOIN 0x118 + +void gpio_config_padcfg(u32 port, u32 padcfg) +{ + write32p(SYS_IOMUX_CFGSAIF_SYSCFG(288), padcfg & 0xFF); +} + +void gpio_config(struct gpio_config config) +{ + uintptr_t reg_shift = 8 * (config.port % 4); + uintptr_t reg_offset = 4 * (config.port / 4); + + u32 doen = config.doen << reg_shift; + u32 dout = config.dout << reg_shift; + + u32 doen_mask = 0x3f << reg_shift; + u32 dout_mask = 0x7f << reg_shift; + + clrsetbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_DOEN + reg_offset), doen_mask, doen & doen_mask); + clrsetbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_DOUT + reg_offset), dout_mask, dout & dout_mask); + + if (config.gpi != GPI_NONE) { + reg_shift = 8 * (config.gpi % 4); + reg_offset = 4 * (config.gpi / 4); + + u32 gpi_mask = 0x7f << reg_shift; + u32 gpi = (config.port + 2) << reg_shift; + + clrsetbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_GPI + reg_offset), gpi_mask, gpi & gpi_mask); + } +} + +//void gpio_set(gpio_t port, int high) +//{ +// +// unintptr_t reg_shift = 8 * (port % 4); +// uintptr_t reg_offset = 4 * (port / 4); +// u32 dout_mask = 0x7f << reg_shift; +// u32 dout = high ? (1 << reg_shift) : 0; +// +// setbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_DOUT + reg_offset), dout & dout_mask); +//} +// +//u32 gpio_get(gpio_t port) +//{ +// uintptr_t reg_mask = (port % 32); +// uintptr_t reg_offset = 4 * (port / 32); +// +// u32 val = read32p(JH7110_SYS_IOMUX + GPIO_GPIOIN + reg_offset); +// +// return !!(val & reg_mask); +//} diff --git a/src/soc/starfive/jh7110/include/soc/addressmap.h b/src/soc/starfive/jh7110/include/soc/addressmap.h new file mode 100644 index 0000000..8cd1ab47 --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/addressmap.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_ADDRESSMAP_H__ +#define __SOC_STARFIVE_JH7110_ADDRESSMAP_H__ + +#define JH7110_CLINT 0x02000000 +#define JH7110_L2LIM 0x08000000 +#define JH7110_UART0 0x10000000 +#define JH7110_UART1 0x10010000 +#define JH7110_UART2 0x10020000 +#define JH7110_QSPI 0x21000000 +#define JH7110_SPI0 0x10060000 +#define JH7110_SPI1 0x10070000 +#define JH7110_SPI2 0x10080000 +#define JH7110_SPI3 0x12070000 +#define JH7110_SPI4 0x12080000 +#define JH7110_SPI5 0x12090000 +#define JH7110_SPI6 0x120A0000 +#define JH7110_DRAM 0x40000000 + +#define JH7110_UART(i) (JH7110_UART0 + 0x1000 * i) + +#define JH7110_BOOT_MODE_SELECT_REG 0x1702002C +#define JH7110_BOOT_MODE_SELECT_MASK 0x3 +# define BOOT_MODE_SELECT_SPI 0 +# define BOOT_MODE_SELECT_MMC2 1 +# define BOOT_MODE_SELECT_MMC1 2 +# define BOOT_MODE_SELECT_UART 3 + +// STG (System-Top-Group) controller +#define STG_SYSCON 0x10240000 +// syscon (system control registers) +#define JH7110_SYSCON 0x13030000 +#define JH7110_SYS_SYSCONSAIF_SYSCFG(i) (JH7110_SYSCON + i) +// syscrg (system control and reset generator) +#define JH7110_SYS_CRG(i) (0x13020000 + i) + + +//TODO remove +# define JH7110_SYSCONSAIF_SYSCFG_32_OFFSET 0x20 +# define JH7110_SYSCONSAIF_U0_PLL_WRAP_PLL0_LOCK_SHIFT 26 +# define JH7110_SYSCONSAIF_U0_PLL_WRAP_PLL0_PD_SHIFT 27 +#define JH7110_SYS_IOMUX 0x13040000 +#define JH7110_AON_CRG(i) (0x17000000 + i) +#define JH7110_AON_SYSCON 0x17010000 +#define JH7110_AON_GPIO 0x17020000 // AON (Always on) multiplexing configuration + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/clock.h b/src/soc/starfive/jh7110/include/soc/clock.h new file mode 100644 index 0000000..6c55a5a --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/clock.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_CLOCK_H__ +#define __SOC_STARFIVE_JH7110_CLOCK_H__ + +void clock_init(void); +void jh7110_pll_init(void); +int clock_get_pclk(void); + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/gpio.h b/src/soc/starfive/jh7110/include/soc/gpio.h new file mode 100644 index 0000000..40fadb6 --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/gpio.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_GPIO_H__ +#define __SOC_STARFIVE_JH7110_GPIO_H__ + +#include <stdint.h> +#include <stdbool.h> + +#define GPIO_DOEN_MASK 0x3F +#define GPIO_DOUT_MASK 0x7F +#define GPIO_DIN_MASK 0x7F + +#define GPIO_IE_SHIFT 0 +#define GPIO_IE_MASK BIT(0) +#define GPIO_DS_SHIFT 1 +#define GPIO_DS_MASK GENMASK(2, 1) +#define GPIO_PU_SHIFT 3 +#define GPIO_PU_MASK BIT(3) +#define GPIO_PD_SHIFT 4 +#define GPIO_PD_MASK BIT(4) +#define GPIO_SLEW_SHIFT 5 +#define GPIO_SLEW_MASK BIT(5) +#define GPIO_SMT_SHIFT 6 +#define GPIO_SMT_MASK BIT(6) +#define GPIO_POS_SHIFT 7 +#define GPIO_POS_MASK BIT(7) + +enum gpio_drive_strength { + GPIO_DS_2 = 0, // 2mA + GPIO_DS_4 = 1, // 4mA + GPIO_DS_8 = 2, // 8mA + GPIO_DS_12 = 3, // 12mA +}; + +enum gpio_pull { + PULL_NONE = 0, + PULL_DOWN = 1, + PULL_UP = 1 +}; + +// ie: interrupt-enable (1: enable, 0: disable) +// ds: drive-strength (00: 2mA, 01: 4mA, 10: 8mA, 11: 12mA) +// pu: pull up (1: enable, 0: disable) +// pd: pull down (1: enable, 0: disable) +// slew: slew rate (0: Slow (Half frequency), 1: Fast) +// smt: Active high Schmitt trigger selector (0: No hysteresis, 1: Schmitt trigger enabled) +// pos: Power-on-Start enabler (1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled) +#define GPIO_PADCFG (ie, ds, pu, pd, slew, smt, pos) \ + ((ie << GPIO_IE_SHIFT ) & GPIO_IE_MASK) | \ + ((ds << GPIO_DS_SHIFT ) & GPIO_DS_MASK) | \ + ((pu << GPIO_PU_SHIFT ) & GPIO_PU_MASK) | \ + ((pd << GPIO_PD_SHIFT ) & GPIO_PD_MASK) | \ + ((slew << GPIO_SLEW_SHIFT) & GPIO_SLEW_MASK) | \ + ((smt << GPIO_SMT_SHIFT ) & GPIO_SMT_MASK) | \ + ((pos << GPIO_POS_SHIFT ) & GPIO_POS_MASK); + +// this is to satisfy src/include/gpio.h +typedef u32 gpio_t; + +struct gpio_config { + gpio_t port; + unsigned int doen; + unsigned int dout; + // contains the GPIO pin number (+2 since GPIO0 and GPIO1 are not available) that is + // attached to a predefined input signal (e.g. the first din register contains the gpio number that is supposed to be mapped to the uart rx input signal) + unsigned int gpi; +}; + +void gpio_config_padcfg(u32 port, u32 padcfg); +void gpio_config(struct gpio_config config); + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h b/src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h new file mode 100644 index 0000000..42ab06c --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * copied from the starfive linux kernel + */ + +#ifndef __JH7110_PINFUNC_H__ +#define __JH7110_PINFUNC_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: function selector + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux dout */ +#define GPOUT_LOW 0 +#define GPOUT_HIGH 1 +#define GPOUT_SYS_WAVE511_UART_TX 2 +#define GPOUT_SYS_CAN0_STBY 3 +#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4 +#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5 +#define GPOUT_SYS_CAN0_TXD 6 +#define GPOUT_SYS_USB_DRIVE_VBUS 7 +#define GPOUT_SYS_QSPI_CS1 8 +#define GPOUT_SYS_SPDIF 9 +#define GPOUT_SYS_HDMI_CEC_SDA 10 +#define GPOUT_SYS_HDMI_DDC_SCL 11 +#define GPOUT_SYS_HDMI_DDC_SDA 12 +#define GPOUT_SYS_WATCHDOG 13 +#define GPOUT_SYS_I2C0_CLK 14 +#define GPOUT_SYS_I2C0_DATA 15 +#define GPOUT_SYS_SDIO0_BACK_END_POWER 16 +#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17 +#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18 +#define GPOUT_SYS_SDIO0_RST 19 +#define GPOUT_SYS_UART0_TX 20 +#define GPOUT_SYS_HIFI4_JTAG_TDO 21 +#define GPOUT_SYS_JTAG_TDO 22 +#define GPOUT_SYS_PDM_MCLK 23 +#define GPOUT_SYS_PWM_CHANNEL0 24 +#define GPOUT_SYS_PWM_CHANNEL1 25 +#define GPOUT_SYS_PWM_CHANNEL2 26 +#define GPOUT_SYS_PWM_CHANNEL3 27 +#define GPOUT_SYS_PWMDAC_LEFT 28 +#define GPOUT_SYS_PWMDAC_RIGHT 29 +#define GPOUT_SYS_SPI0_CLK 30 +#define GPOUT_SYS_SPI0_FSS 31 +#define GPOUT_SYS_SPI0_TXD 32 +#define GPOUT_SYS_GMAC_PHYCLK 33 +#define GPOUT_SYS_I2SRX_BCLK 34 +#define GPOUT_SYS_I2SRX_LRCK 35 +#define GPOUT_SYS_I2STX0_BCLK 36 +#define GPOUT_SYS_I2STX0_LRCK 37 +#define GPOUT_SYS_MCLK 38 +#define GPOUT_SYS_TDM_CLK 39 +#define GPOUT_SYS_TDM_SYNC 40 +#define GPOUT_SYS_TDM_TXD 41 +#define GPOUT_SYS_TRACE_DATA0 42 +#define GPOUT_SYS_TRACE_DATA1 43 +#define GPOUT_SYS_TRACE_DATA2 44 +#define GPOUT_SYS_TRACE_DATA3 45 +#define GPOUT_SYS_TRACE_REF 46 +#define GPOUT_SYS_CAN1_STBY 47 +#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48 +#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49 +#define GPOUT_SYS_CAN1_TXD 50 +#define GPOUT_SYS_I2C1_CLK 51 +#define GPOUT_SYS_I2C1_DATA 52 +#define GPOUT_SYS_SDIO1_BACK_END_POWER 53 +#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54 +#define GPOUT_SYS_SDIO1_CLK 55 +#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56 +#define GPOUT_SYS_SDIO1_CMD 57 +#define GPOUT_SYS_SDIO1_DATA0 58 +#define GPOUT_SYS_SDIO1_DATA1 59 +#define GPOUT_SYS_SDIO1_DATA2 60 +#define GPOUT_SYS_SDIO1_DATA3 61 +#define GPOUT_SYS_SDIO1_DATA4 63 +#define GPOUT_SYS_SDIO1_DATA5 63 +#define GPOUT_SYS_SDIO1_DATA6 64 +#define GPOUT_SYS_SDIO1_DATA7 65 +#define GPOUT_SYS_SDIO1_RST 66 +#define GPOUT_SYS_UART1_RTS 67 +#define GPOUT_SYS_UART1_TX 68 +#define GPOUT_SYS_I2STX1_SDO0 69 +#define GPOUT_SYS_I2STX1_SDO1 70 +#define GPOUT_SYS_I2STX1_SDO2 71 +#define GPOUT_SYS_I2STX1_SDO3 72 +#define GPOUT_SYS_SPI1_CLK 73 +#define GPOUT_SYS_SPI1_FSS 74 +#define GPOUT_SYS_SPI1_TXD 75 +#define GPOUT_SYS_I2C2_CLK 76 +#define GPOUT_SYS_I2C2_DATA 77 +#define GPOUT_SYS_UART2_RTS 78 +#define GPOUT_SYS_UART2_TX 79 +#define GPOUT_SYS_SPI2_CLK 80 +#define GPOUT_SYS_SPI2_FSS 81 +#define GPOUT_SYS_SPI2_TXD 82 +#define GPOUT_SYS_I2C3_CLK 83 +#define GPOUT_SYS_I2C3_DATA 84 +#define GPOUT_SYS_UART3_TX 85 +#define GPOUT_SYS_SPI3_CLK 86 +#define GPOUT_SYS_SPI3_FSS 87 +#define GPOUT_SYS_SPI3_TXD 88 +#define GPOUT_SYS_I2C4_CLK 89 +#define GPOUT_SYS_I2C4_DATA 90 +#define GPOUT_SYS_UART4_RTS 91 +#define GPOUT_SYS_UART4_TX 92 +#define GPOUT_SYS_SPI4_CLK 93 +#define GPOUT_SYS_SPI4_FSS 94 +#define GPOUT_SYS_SPI4_TXD 95 +#define GPOUT_SYS_I2C5_CLK 96 +#define GPOUT_SYS_I2C5_DATA 97 +#define GPOUT_SYS_UART5_RTS 98 +#define GPOUT_SYS_UART5_TX 99 +#define GPOUT_SYS_SPI5_CLK 100 +#define GPOUT_SYS_SPI5_FSS 101 +#define GPOUT_SYS_SPI5_TXD 102 +#define GPOUT_SYS_I2C6_CLK 103 +#define GPOUT_SYS_I2C6_DATA 104 +#define GPOUT_SYS_SPI6_CLK 105 +#define GPOUT_SYS_SPI6_FSS 106 +#define GPOUT_SYS_SPI6_TXD 107 + +/* aon_iomux dout */ +#define GPOUT_AON_CLK_32K_OUT 2 +#define GPOUT_AON_PTC0_PWM4 3 +#define GPOUT_AON_PTC0_PWM5 4 +#define GPOUT_AON_PTC0_PWM6 5 +#define GPOUT_AON_PTC0_PWM7 6 +#define GPOUT_AON_CLK_GCLK0 7 +#define GPOUT_AON_CLK_GCLK1 8 +#define GPOUT_AON_CLK_GCLK2 9 + +/* sys_iomux doen */ +#define GPOEN_ENABLE 0 +#define GPOEN_DISABLE 1 +#define GPOEN_SYS_HDMI_CEC_SDA 2 +#define GPOEN_SYS_HDMI_DDC_SCL 3 +#define GPOEN_SYS_HDMI_DDC_SDA 4 +#define GPOEN_SYS_I2C0_CLK 5 +#define GPOEN_SYS_I2C0_DATA 6 +#define GPOEN_SYS_HIFI4_JTAG_TDO 7 +#define GPOEN_SYS_JTAG_TDO 8 +#define GPOEN_SYS_PWM0_CHANNEL0 9 +#define GPOEN_SYS_PWM0_CHANNEL1 10 +#define GPOEN_SYS_PWM0_CHANNEL2 11 +#define GPOEN_SYS_PWM0_CHANNEL3 12 +#define GPOEN_SYS_SPI0_NSSPCTL 13 +#define GPOEN_SYS_SPI0_NSSP 14 +#define GPOEN_SYS_TDM_SYNC 15 +#define GPOEN_SYS_TDM_TXD 16 +#define GPOEN_SYS_I2C1_CLK 17 +#define GPOEN_SYS_I2C1_DATA 18 +#define GPOEN_SYS_SDIO1_CMD 19 +#define GPOEN_SYS_SDIO1_DATA0 20 +#define GPOEN_SYS_SDIO1_DATA1 21 +#define GPOEN_SYS_SDIO1_DATA2 22 +#define GPOEN_SYS_SDIO1_DATA3 23 +#define GPOEN_SYS_SDIO1_DATA4 24 +#define GPOEN_SYS_SDIO1_DATA5 25 +#define GPOEN_SYS_SDIO1_DATA6 26 +#define GPOEN_SYS_SDIO1_DATA7 27 +#define GPOEN_SYS_SPI1_NSSPCTL 28 +#define GPOEN_SYS_SPI1_NSSP 29 +#define GPOEN_SYS_I2C2_CLK 30 +#define GPOEN_SYS_I2C2_DATA 31 +#define GPOEN_SYS_SPI2_NSSPCTL 32 +#define GPOEN_SYS_SPI2_NSSP 33 +#define GPOEN_SYS_I2C3_CLK 34 +#define GPOEN_SYS_I2C3_DATA 35 +#define GPOEN_SYS_SPI3_NSSPCTL 36 +#define GPOEN_SYS_SPI3_NSSP 37 +#define GPOEN_SYS_I2C4_CLK 38 +#define GPOEN_SYS_I2C4_DATA 39 +#define GPOEN_SYS_SPI4_NSSPCTL 40 +#define GPOEN_SYS_SPI4_NSSP 41 +#define GPOEN_SYS_I2C5_CLK 42 +#define GPOEN_SYS_I2C5_DATA 43 +#define GPOEN_SYS_SPI5_NSSPCTL 44 +#define GPOEN_SYS_SPI5_NSSP 45 +#define GPOEN_SYS_I2C6_CLK 46 +#define GPOEN_SYS_I2C6_DATA 47 +#define GPOEN_SYS_SPI6_NSSPCTL 48 +#define GPOEN_SYS_SPI6_NSSP 49 + +/* aon_iomux doen */ +#define GPOEN_AON_PTC0_OE_N_4 2 +#define GPOEN_AON_PTC0_OE_N_5 3 +#define GPOEN_AON_PTC0_OE_N_6 4 +#define GPOEN_AON_PTC0_OE_N_7 5 + +/* sys_iomux gin */ +#define GPI_NONE 255 +#define GPI_SYS_WAVE511_UART_RX 0 +#define GPI_SYS_CAN0_RXD 1 +#define GPI_SYS_USB_OVERCURRENT 2 +#define GPI_SYS_SPDIF 3 +#define GPI_SYS_JTAG_RST 4 +#define GPI_SYS_HDMI_CEC_SDA 5 +#define GPI_SYS_HDMI_DDC_SCL 6 +#define GPI_SYS_HDMI_DDC_SDA 7 +#define GPI_SYS_HDMI_HPD 8 +#define GPI_SYS_I2C0_CLK 9 +#define GPI_SYS_I2C0_DATA 10 +#define GPI_SYS_SDIO0_CD 11 +#define GPI_SYS_SDIO0_INT 12 +#define GPI_SYS_SDIO0_WP 13 +#define GPI_SYS_UART0_RX 14 +#define GPI_SYS_HIFI4_JTAG_TCK 15 +#define GPI_SYS_HIFI4_JTAG_TDI 16 +#define GPI_SYS_HIFI4_JTAG_TMS 17 +#define GPI_SYS_HIFI4_JTAG_RST 18 +#define GPI_SYS_JTAG_TDI 19 +#define GPI_SYS_JTAG_TMS 20 +#define GPI_SYS_PDM_DMIC0 21 +#define GPI_SYS_PDM_DMIC1 22 +#define GPI_SYS_I2SRX_SDIN0 23 +#define GPI_SYS_I2SRX_SDIN1 24 +#define GPI_SYS_I2SRX_SDIN2 25 +#define GPI_SYS_SPI0_CLK 26 +#define GPI_SYS_SPI0_FSS 27 +#define GPI_SYS_SPI0_RXD 28 +#define GPI_SYS_JTAG_TCK 29 +#define GPI_SYS_MCLK_EXT 30 +#define GPI_SYS_I2SRX_BCLK 31 +#define GPI_SYS_I2SRX_LRCK 32 +#define GPI_SYS_I2STX1_BCLK 33 +#define GPI_SYS_I2STX1_LRCK 34 +#define GPI_SYS_TDM_CLK 35 +#define GPI_SYS_TDM_RXD 36 +#define GPI_SYS_TDM_SYNC 37 +#define GPI_SYS_CAN1_RXD 38 +#define GPI_SYS_I2C1_CLK 39 +#define GPI_SYS_I2C1_DATA 40 +#define GPI_SYS_SDIO1_CD 41 +#define GPI_SYS_SDIO1_INT 42 +#define GPI_SYS_SDIO1_WP 43 +#define GPI_SYS_SDIO1_CMD 44 +#define GPI_SYS_SDIO1_DATA0 45 +#define GPI_SYS_SDIO1_DATA1 46 +#define GPI_SYS_SDIO1_DATA2 47 +#define GPI_SYS_SDIO1_DATA3 48 +#define GPI_SYS_SDIO1_DATA4 49 +#define GPI_SYS_SDIO1_DATA5 50 +#define GPI_SYS_SDIO1_DATA6 51 +#define GPI_SYS_SDIO1_DATA7 52 +#define GPI_SYS_SDIO1_STRB 53 +#define GPI_SYS_UART1_CTS 54 +#define GPI_SYS_UART1_RX 55 +#define GPI_SYS_SPI1_CLK 56 +#define GPI_SYS_SPI1_FSS 57 +#define GPI_SYS_SPI1_RXD 58 +#define GPI_SYS_I2C2_CLK 59 +#define GPI_SYS_I2C2_DATA 60 +#define GPI_SYS_UART2_CTS 61 +#define GPI_SYS_UART2_RX 62 +#define GPI_SYS_SPI2_CLK 63 +#define GPI_SYS_SPI2_FSS 64 +#define GPI_SYS_SPI2_RXD 65 +#define GPI_SYS_I2C3_CLK 66 +#define GPI_SYS_I2C3_DATA 67 +#define GPI_SYS_UART3_RX 68 +#define GPI_SYS_SPI3_CLK 69 +#define GPI_SYS_SPI3_FSS 70 +#define GPI_SYS_SPI3_RXD 71 +#define GPI_SYS_I2C4_CLK 72 +#define GPI_SYS_I2C4_DATA 73 +#define GPI_SYS_UART4_CTS 74 +#define GPI_SYS_UART4_RX 75 +#define GPI_SYS_SPI4_CLK 76 +#define GPI_SYS_SPI4_FSS 77 +#define GPI_SYS_SPI4_RXD 78 +#define GPI_SYS_I2C5_CLK 79 +#define GPI_SYS_I2C5_DATA 80 +#define GPI_SYS_UART5_CTS 81 +#define GPI_SYS_UART5_RX 82 +#define GPI_SYS_SPI5_CLK 83 +#define GPI_SYS_SPI5_FSS 84 +#define GPI_SYS_SPI5_RXD 85 +#define GPI_SYS_I2C6_CLK 86 +#define GPI_SYS_I2C6_DATA 87 +#define GPI_SYS_SPI6_CLK 88 +#define GPI_SYS_SPI6_FSS 89 +#define GPI_SYS_SPI6_RXD 90 + +/* aon_iomux gin */ +#define GPI_AON_PMU_GPIO_WAKEUP_0 0 +#define GPI_AON_PMU_GPIO_WAKEUP_1 1 +#define GPI_AON_PMU_GPIO_WAKEUP_2 2 +#define GPI_AON_PMU_GPIO_WAKEUP_3 3 + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/jh7110.dtsi b/src/soc/starfive/jh7110/include/soc/jh7110.dtsi new file mode 100644 index 0000000..11cac5f --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/jh7110.dtsi @@ -0,0 +1,1360 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + */ + +/dts-v1/; +#include <dt-bindings/clock/starfive,jh7110-crg.h> +#include <dt-bindings/power/starfive,jh7110-pmu.h> +#include <dt-bindings/reset/starfive,jh7110-crg.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "starfive,jh7110"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + S7_0: cpu@0 { + compatible = "sifive,s7", "riscv"; + reg = <0>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <16384>; + next-level-cache = <&ccache>; + riscv,isa = "rv64imac_zba_zbb"; + status = "disabled"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_1: cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_2: cpu@2 { + compatible = "sifive,u74-mc", "riscv"; + reg = <2>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_3: cpu@3 { + compatible = "sifive,u74-mc", "riscv"; + reg = <3>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_4: cpu@4 { + compatible = "sifive,u74-mc", "riscv"; + reg = <4>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&S7_0>; + }; + + core1 { + cpu = <&U74_1>; + }; + + core2 { + cpu = <&U74_2>; + }; + + core3 { + cpu = <&U74_3>; + }; + + core4 { + cpu = <&U74_4>; + }; + }; + }; + }; + + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + + display: display-subsystem { + compatible = "starfive,display-subsystem"; + + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>; + clock-names = "noc_bus", "dc_core", "axi_core", "ahb"; + resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>, + <&voutcrg JH7110_VOUTRST_DC8200_CORE>; + reset-names = "axi","ahb", "core"; + }; + + dsi_encoder: dsi_encoder { + compatible = "starfive,dsi-encoder"; + starfive,syscon = <&vout_syscon 0x8 0x08>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <15000>; + + thermal-sensors = <&sfctemp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + dvp_clk: dvp-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; + + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rgmii_rxin"; + #clock-cells = <0>; + }; + + gmac0_rmii_refin: gmac0-rmii-refin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rmii_refin"; + #clock-cells = <0>; + }; + + gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac1_rgmii_rxin"; + #clock-cells = <0>; + }; + + gmac1_rmii_refin: gmac1-rmii-refin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac1_rmii_refin"; + #clock-cells = <0>; + }; + + hdmitx0_pixelclk: hdmitx0-pixel-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + + i2srx_bclk_ext: i2srx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_bclk_ext"; + #clock-cells = <0>; + }; + + i2srx_lrck_ext: i2srx-lrck-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_lrck_ext"; + #clock-cells = <0>; + }; + + i2stx_bclk_ext: i2stx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2stx_bclk_ext"; + #clock-cells = <0>; + }; + + i2stx_lrck_ext: i2stx-lrck-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2stx_lrck_ext"; + #clock-cells = <0>; + }; + + mclk_ext: mclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "mclk_ext"; + #clock-cells = <0>; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc"; + #clock-cells = <0>; + }; + + rtc_osc: rtc-oscillator { + compatible = "fixed-clock"; + clock-output-names = "rtc_osc"; + #clock-cells = <0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <15>; + snps,rd_osr_lmt = <15>; + snps,blen = <256 128 64 32 0 0 0>; + }; + + tdm_ext: tdm-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "tdm_ext"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: timer@2000000 { + compatible = "starfive,jh7110-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + ccache: cache-controller@2010000 { + compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; + reg = <0x0 0x2010000 0x0 0x4000>; + interrupts = <1>, <3>, <4>, <2>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + }; + + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <136>; + }; + + uart0: serial@10000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, + <&syscrg JH7110_SYSCLK_UART0_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART0_APB>; + interrupts = <32>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@10010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, + <&syscrg JH7110_SYSCLK_UART1_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART1_APB>; + interrupts = <33>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@10020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, + <&syscrg JH7110_SYSCLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART2_APB>; + interrupts = <34>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c0: i2c@10030000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10030000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C0_APB>; + interrupts = <35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@10040000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C1_APB>; + interrupts = <36>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@10050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10050000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C2_APB>; + interrupts = <37>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@10060000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10060000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>, + <&syscrg JH7110_SYSCLK_SPI0_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI0_APB>; + interrupts = <38>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@10070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>, + <&syscrg JH7110_SYSCLK_SPI1_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI1_APB>; + interrupts = <39>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@10080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>, + <&syscrg JH7110_SYSCLK_SPI2_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI2_APB>; + interrupts = <40>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tdm: tdm@10090000 { + compatible = "starfive,jh7110-tdm"; + reg = <0x0 0x10090000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, + <&syscrg JH7110_SYSCLK_TDM_APB>, + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, + <&syscrg JH7110_SYSCLK_TDM_TDM>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&tdm_ext>; + clock-names = "tdm_ahb", "tdm_apb", + "tdm_internal", "tdm", + "mclk_inner", "tdm_ext"; + resets = <&syscrg JH7110_SYSRST_TDM_AHB>, + <&syscrg JH7110_SYSRST_TDM_APB>, + <&syscrg JH7110_SYSRST_TDM_CORE>; + dmas = <&dma 20>, <&dma 21>; + dma-names = "rx","tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pwmdac: pwmdac@100b0000 { + compatible = "starfive,jh7110-pwmdac"; + reg = <0x0 0x100b0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>, + <&syscrg JH7110_SYSCLK_PWMDAC_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>; + dmas = <&dma 22>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2srx: i2s@100e0000 { + compatible = "starfive,jh7110-i2srx"; + reg = <0x0 0x100e0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2SRX_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>, + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>, + <&i2srx_bclk_ext>, + <&i2srx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>, + <&syscrg JH7110_SYSRST_I2SRX_BCLK>; + dmas = <0>, <&dma 24>; + dma-names = "tx", "rx"; + starfive,syscon = <&sys_syscon 0x18 0x2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, + <&syscrg JH7110_SYSCLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART3_APB>; + interrupts = <45>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@12010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, + <&syscrg JH7110_SYSCLK_UART4_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART4_APB>; + interrupts = <46>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@12020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, + <&syscrg JH7110_SYSCLK_UART5_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART5_APB>; + interrupts = <47>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c3: i2c@12030000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12030000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C3_APB>; + interrupts = <48>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@12040000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C4_APB>; + interrupts = <49>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@12050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12050000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C5_APB>; + interrupts = <50>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@12060000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12060000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C6_APB>; + interrupts = <51>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@12070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>, + <&syscrg JH7110_SYSCLK_SPI3_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI3_APB>; + interrupts = <52>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@12080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>, + <&syscrg JH7110_SYSCLK_SPI4_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI4_APB>; + interrupts = <53>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@12090000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12090000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>, + <&syscrg JH7110_SYSCLK_SPI5_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI5_APB>; + interrupts = <54>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@120a0000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x120A0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>, + <&syscrg JH7110_SYSCLK_SPI6_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI6_APB>; + interrupts = <55>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2stx0: i2s@120b0000 { + compatible = "starfive,jh7110-i2stx0"; + reg = <0x0 0x120b0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX0_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner","mclk_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>, + <&syscrg JH7110_SYSRST_I2STX0_BCLK>; + dmas = <&dma 47>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2stx1: i2s@120c0000 { + compatible = "starfive,jh7110-i2stx1"; + reg = <0x0 0x120c0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX1_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2STX1_BCLK>, + <&syscrg JH7110_SYSCLK_I2STX1_LRCK>, + <&i2stx_bclk_ext>, + <&i2stx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX1_APB>, + <&syscrg JH7110_SYSRST_I2STX1_BCLK>; + dmas = <&dma 48>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pwm: pwm@120d0000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x0 0x120d0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + + sfctemp: temperature-sensor@120e0000 { + compatible = "starfive,jh7110-temp"; + reg = <0x0 0x120e0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>, + <&syscrg JH7110_SYSCLK_TEMP_APB>; + clock-names = "sense", "bus"; + resets = <&syscrg JH7110_SYSRST_TEMP_CORE>, + <&syscrg JH7110_SYSRST_TEMP_APB>; + reset-names = "sense", "bus"; + #thermal-sensor-cells = <0>; + }; + + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000>, + <0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + status = "disabled"; + }; + + syscrg: clock-controller@13020000 { + compatible = "starfive,jh7110-syscrg"; + reg = <0x0 0x13020000 0x0 0x10000>; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL1_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + + sysgpio: pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; + resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; + interrupts = <86>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + timer@13050000 { + compatible = "starfive,jh7110-timer"; + reg = <0x0 0x13050000 0x0 0x10000>; + interrupts = <69>, <70>, <71>, <72>; + clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>, + <&syscrg JH7110_SYSCLK_TIMER0>, + <&syscrg JH7110_SYSCLK_TIMER1>, + <&syscrg JH7110_SYSCLK_TIMER2>, + <&syscrg JH7110_SYSCLK_TIMER3>; + clock-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + resets = <&syscrg JH7110_SYSRST_TIMER_APB>, + <&syscrg JH7110_SYSRST_TIMER0>, + <&syscrg JH7110_SYSRST_TIMER1>, + <&syscrg JH7110_SYSRST_TIMER2>, + <&syscrg JH7110_SYSRST_TIMER3>; + reset-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + }; + + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + + crypto: crypto@16000000 { + compatible = "starfive,jh7110-crypto"; + reg = <0x0 0x16000000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + interrupts = <28>; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + dmas = <&sdma 1 2>, <&sdma 0 2>; + dma-names = "tx", "rx"; + }; + + sdma: dma-controller@16008000 { + compatible = "arm,pl080", "arm,primecell"; + arm,primecell-periphid = <0x00041080>; + reg = <0x0 0x16008000 0x0 0x4000>; + interrupts = <29>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>; + clock-names = "apb_pclk"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + interrupts = <30>; + }; + + mmc0: mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; + status = "disabled"; + }; + + mmc1: mmc@16020000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; + reset-names = "reset"; + interrupts = <75>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; + status = "disabled"; + }; + + gmac0: ethernet@16030000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16030000 0x0 0x10000>; + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, + <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, + <&aoncrg JH7110_AONRST_GMAC0_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <7>, <6>, <5>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&aon_syscon 0xc 0x12>; + status = "disabled"; + }; + + gmac1: ethernet@16040000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, + <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, + <&syscrg JH7110_SYSRST_GMAC1_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <78>, <77>, <76>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&sys_syscon 0x90 0x2>; + status = "disabled"; + }; + + dma: dma-controller@16050000 { + compatible = "starfive,jh7110-axi-dma"; + reg = <0x0 0x16050000 0x0 0x10000>; + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, + <&stgcrg JH7110_STGCLK_DMA1P_AHB>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, + <&stgcrg JH7110_STGRST_DMA1P_AHB>; + interrupts = <73>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; + + aoncrg: clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x0 0x17000000 0x0 0x10000>; + clocks = <&osc>, <&gmac0_rmii_refin>, + <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, + <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk", + "rtc_osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + + aongpio: pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x0 0x17020000 0x0 0x10000>; + resets = <&aoncrg JH7110_AONRST_IOMUX>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x0 0x17030000 0x0 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; + + csi2rx: csi@19800000 { + compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x19800000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>, + <&ispcrg JH7110_ISPCLK_VIN_APB>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + resets = <&ispcrg JH7110_ISPRST_VIN_SYS>, + <&ispcrg JH7110_ISPRST_VIN_APB>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>; + reset-names = "sys", "reg_bank", + "pixel_if0", "pixel_if1", + "pixel_if2", "pixel_if3"; + phys = <&csi_phy>; + phy-names = "dphy"; + status = "disabled"; + }; + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x0 0x19810000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; + + csi_phy: phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x0 0x19820000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, + <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>; + power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>; + #phy-cells = <0>; + }; + + camss: isp@19840000 { + compatible = "starfive,jh7110-camss"; + reg = <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>; + reg-names = "syscon", "isp"; + clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPCLK_DVP_INV>, + <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>, + <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>; + clock-names = "apb_func", "wrapper_clk_c", "dvp_inv", + "axiwr", "mipi_rx0_pxl", "ispcore_2x", + "isp_axi"; + resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>, + <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>, + <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>; + reset-names = "wrapper_p", "wrapper_c", "axird", + "axiwr", "isp_top_n", "isp_top_axi"; + power-domains = <&pwrc JH7110_PD_ISP>; + interrupts = <92>, <87>, <90>, <88>; + status = "disabled"; + }; + + dc8200: lcd-controller@29400000 { + compatible = "starfive,jh7110-dc8200"; + reg = <0x0 0x29400000 0x0 0x100>, + <0x0 0x29400800 0x0 0x2000>; + interrupts = <95>; + clocks = <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>, + <&hdmitx0_pixelclk>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX>; + clock-names = "channel0", "channel1", + "hdmi_tx", "dc_parent"; + }; + + hdmi: hdmi@29590000 { + compatible = "starfive,jh7110-inno-hdmi"; + reg = <0x0 0x29590000 0x0 0x4000>; + interrupts = <99>; + + clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>; + clock-names = "sysclk", "mclk", "bclk"; + resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + #sound-dai-cells = <0>; + }; + + vout_syscon: syscon@295b0000 { + compatible = "starfive,jh7110-vout-syscon", "syscon"; + reg = <0 0x295b0000 0 0x90>; + }; + + voutcrg: clock-controller@295c0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x0 0x295c0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; + + pcie0: pcie@940000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0x40000000 0x0 0x1000000>, + <0x0 0x2b000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE0_TL>, + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE0_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE0_BRG>, + <&stgcrg JH7110_STGRST_PCIE0_CORE>, + <&stgcrg JH7110_STGRST_PCIE0_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@9c0000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0xc0000000 0x0 0x1000000>, + <0x0 0x2c000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + interrupts = <57>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE1_TL>, + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE1_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE1_BRG>, + <&stgcrg JH7110_STGRST_PCIE1_CORE>, + <&stgcrg JH7110_STGRST_PCIE1_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; +}; diff --git a/src/soc/starfive/jh7110/include/soc/sdram.h b/src/soc/starfive/jh7110/include/soc/sdram.h new file mode 100644 index 0000000..bb9dbba --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/sdram.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_SDRAM_H__ +#define __SOC_STARFIVE_JH7110_SDRAM_H__ + +#include <stdint.h> +#include <types.h> + +void sdram_init(size_t dram_size); +size_t sdram_size(void); + +#endif diff --git a/src/soc/starfive/jh7110/memlayout.ld b/src/soc/starfive/jh7110/memlayout.ld new file mode 100644 index 0000000..39d72be --- /dev/null +++ b/src/soc/starfive/jh7110/memlayout.ld @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <soc/addressmap.h> + +#include <arch/header.ld> + +SECTIONS +{ + SRAM_START(JH7110_L2LIM) + /* The 64K size is not allocated. It's just for basic size checking. */ + BOOTBLOCK(JH7110_L2LIM, 64K) + CAR_STACK(JH7110_L2LIM + 64K, 12K) // considering each harts stack is a pagesize (4K), we can potentially have up to 16 harts regarding stack space //TODO reduce it, since fu740 doesn't even have/support 16 harts + PRERAM_CBMEM_CONSOLE(JH7110_L2LIM + 76K, 8K) + CBFS_MCACHE(JH7110_L2LIM + 84K, 8K) + FMAP_CACHE(JH7110_L2LIM + 92K, 2K) + PRERAM_CBFS_CACHE(JH7110_L2LIM + 94K, 128K) + SRAM_END(JH7110_L2LIM + 2M) + + DRAM_START(JH7110_DRAM) + OPENSBI(JH7110_DRAM, 512K) + /* The 512K size is not allocated. It's just for basic size checking. */ + RAMSTAGE(JH7110_DRAM + 512K, 512K) + MEM_STACK(JH7110_DRAM + 512K + 512K, 20K) + POSTRAM_CBFS_CACHE(JH7110_DRAM + 512K + 512K + 20K, 32M - 2M) +} diff --git a/src/soc/starfive/jh7110/sdram.c b/src/soc/starfive/jh7110/sdram.c new file mode 100644 index 0000000..b4bef3d --- /dev/null +++ b/src/soc/starfive/jh7110/sdram.c @@ -0,0 +1,2971 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * Author: yanhong yanhong.wang@starfivetech.com + * + * Based on starfives u-boot fork + */ + +#ifndef _STARFIVE_SDRAM_H +#define _STARFIVE_SDRAM_H + +#include <arch/mmio.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/sdram.h> +#include <stdint.h> +#include <stddef.h> +#include <delay.h> + +#define SEC_CTRL_ADDR 0x1000 +#define PHY_BASE_ADDR 0x2000 +#define PHY_AC_BASE_ADDR 0x4000 + +#define DDR_BUS_SHIFT 24 +#define DDR_BUS_MASK GENMASK(29, 24) +#define DDR_BUS_OFFSET 0xAC +#define DDR_AXI_SHIFT 31 +#define DDR_AXI_MASK BIT(31) +#define DDR_AXI_OFFSET 0xB0 + +#define DDR_BUS_OSC_DIV2 0 +#define DDR_BUS_PLL1_DIV2 1 +#define DDR_BUS_PLL1_DIV4 2 +#define DDR_BUS_PLL1_DIV8 3 +#define DDR_AXI_DISABLE 0 +#define DDR_AXI_ENABLE 1 + +#define OFFSET_SEL BIT(31) +#define REG2G BIT(30) // registers that are written if DRAM is 2G big +#define REG4G BIT(29) // registers that are written if DRAM is 4G big +#define REG8G BIT(28) // registers that are written if DRAM is 8G big +#define F_ADDSET BIT(2) +#define F_SET BIT(1) +#define F_CLRSET BIT(0) +#define REGALL (REG2G | REG4G | REG8G) +#define REGSETALL (F_SET | REGALL) +#define REGCLRSETALL (F_CLRSET | REGALL) +#define REGADDSETALL (F_ADDSET | REGALL) + +//TODO negate mask in all arrays so I can properly use clrsetbits32p +//#define DDR_REG_TRIGGER(addr, mask, value) \ +// clrsetbits32p(addr, mask, value) +#define DDR_REG_TRIGGER(addr, mask, value) \ + write32p((addr), (read32p(addr) & (mask)) | (value)) + +#define DDR_BUS_REG_SET(val) \ + clrsetbits32p(JH7110_SYS_CRG(DDR_BUS_OFFSET), \ + DDR_BUS_MASK, \ + (val << DDR_BUS_SHIFT) & DDR_BUS_MASK) + +struct ddr_reg_cfg { + u32 offset; // offset in bytes + u32 mask; + u32 val; + u32 flag; +}; + +static const struct ddr_reg_cfg ddr_csr_cfg[] = { + {0x00000000, 0x00000000, 0x00000001, REGSETALL}, + {0x00000f00, 0x00000000, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0x00000f00, 0x00000000, 0x40001030, (OFFSET_SEL | F_SET | REG2G)}, + {0x00000f04, 0x00000000, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0x00000f04, 0x00000000, 0x00800001, (OFFSET_SEL | F_SET | REG2G)}, + {0x00000f10, 0x00000000, 0x00400000, (OFFSET_SEL | REGSETALL)}, + {0x00000f14, 0x00000000, 0x043fffff, (OFFSET_SEL | REGSETALL)}, + {0x00000f18, 0x00000000, 0x00000000, (OFFSET_SEL | REGSETALL)}, + {0x00000f30, 0x00000000, 0x1f000041, (OFFSET_SEL | REGSETALL)}, + {0x00000f34, 0x00000000, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0x00000110, 0x00000000, 0xc0000001, (OFFSET_SEL | REGSETALL)}, + {0x00000114, 0x00000000, 0xffffffff, (OFFSET_SEL | REGSETALL)}, + {0x0000010c, 0x00000000, 0x00000505, REGSETALL}, + {0x0000011c, 0x00000000, 0x00000000, REGSETALL}, + {0x00000500, 0x00000000, 0x00000201, REGSETALL}, + {0x00000514, 0x00000000, 0x00000100, REGSETALL}, + {0x000006a8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000ea8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000504, 0x00000000, 0x40000000, REGSETALL} +}; + +static const struct ddr_reg_cfg ddr_csr_cfg1[] = { + {0x00000310, 0x00000000, 0x00020000, REGSETALL}, + {0x00000310, 0x00000000, 0x00020001, REGSETALL}, + {0x00000600, 0x00000000, 0x002e0176, REGSETALL}, + {0x00000604, 0x00000000, 0x002e0176, REGSETALL}, + {0x00000608, 0x00000000, 0x001700bb, REGSETALL}, + {0x0000060c, 0x00000000, 0x000b005d, REGSETALL}, + {0x00000610, 0x00000000, 0x0005002e, REGSETALL}, + {0x00000614, 0x00000000, 0x00020017, REGSETALL}, + {0x00000618, 0x00000000, 0x00020017, REGSETALL}, + {0x0000061c, 0x00000000, 0x00020017, REGSETALL}, + {0x00000678, 0x00000000, 0x00000019, REGSETALL}, + {0x00000100, 0x00000000, 0x000000f8, REGSETALL}, + {0x00000620, 0x00000000, 0x03030404, REGSETALL}, + {0x00000624, 0x00000000, 0x04030505, REGSETALL}, + {0x00000628, 0x00000000, 0x07030884, REGSETALL}, + {0x0000062c, 0x00000000, 0x13150401, REGSETALL}, + {0x00000630, 0x00000000, 0x17150604, REGSETALL}, + {0x00000634, 0x00000000, 0x00110000, REGSETALL}, + {0x00000638, 0x00000000, 0x200a0a08, REGSETALL}, + {0x0000063c, 0x00000000, 0x1730f803, REGSETALL}, + {0x00000640, 0x00000000, 0x000a0c00, REGSETALL}, + {0x00000644, 0x00000000, 0xa005000a, REGSETALL}, + {0x00000648, 0x00000000, 0x00000000, REGSETALL}, + {0x0000064c, 0x00000000, 0x00081306, REGSETALL}, + {0x00000650, 0x00000000, 0x04070304, REGSETALL}, + {0x00000654, 0x00000000, 0x00000404, REGSETALL}, + {0x00000658, 0x00000000, 0x00000060, REGSETALL}, + {0x0000065c, 0x00000000, 0x00030008, REGSETALL}, + {0x00000660, 0x00000000, 0x00000000, REGSETALL}, + {0x00000680, 0x00000000, 0x00000603, REGSETALL}, + {0x00000684, 0x00000000, 0x01000202, REGSETALL}, + {0x00000688, 0x00000000, 0x0413040d, REGSETALL}, + {0x0000068c, 0x00000000, 0x20002420, REGSETALL}, + {0x00000690, 0x00000000, 0x00140000, REGSETALL}, + {0x0000069c, 0x00000000, 0x01240074, REGSETALL}, + {0x000006a0, 0x00000000, 0x00000000, REGSETALL}, + {0x000006a4, 0x00000000, 0x20240c00, REGSETALL}, + {0x000006a8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000004, 0x00000000, 0x30010006, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10010006, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30020000, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10020000, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30030031, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10030031, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x300b0033, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x100b0033, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30160016, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10160016, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000010, 0x00000000, 0x00000010, REGSETALL}, + {0x00000014, 0x00000000, 0x00000001, REGSETALL}, +}; + +static const struct ddr_reg_cfg ddr_csr_cfg2[] = { + {0xb8, 0xf0ffffff, 0x3000000, REGCLRSETALL}, + {0x84, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb4, 0xffffffff, 0x1, REGCLRSETALL}, + {0x248, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x300, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0xb0, 0xffffffff, 0x100, REGCLRSETALL}, + {0xb8, 0xFFF0FFFF, 0x30000, REGCLRSETALL}, + {0x84, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xac, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xac, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xffffffff, 0x1, REGCLRSETALL}, + {0x248, 0xffffffff, 0x30000, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x3, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x30000, REGCLRSETALL}, + {0x250, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x254, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x258, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0xac, 0xffffffff, 0x100, REGCLRSETALL}, + {0x10c, 0xFFFFF0FF, 0x300, REGCLRSETALL}, + {0x110, 0xFFFFFEFF, 0x0, REGCLRSETALL}, + {0x11c, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0x11c, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0x120, 0xffffffff, 0x100, REGCLRSETALL}, + {0x2d0, 0xffffffff, 0x300, REGCLRSETALL}, + {0x2dc, 0xffffffff, 0x300, REGCLRSETALL}, + {0x2e8, 0xffffffff, 0x300, REGCLRSETALL}, +}; + +static const struct ddr_reg_cfg ddr_csr_cfg3[] = { + {0x00000100, 0x00000000, 0x000000e0, REGSETALL}, + {0x00000620, 0x00000000, 0x04041417, REGSETALL}, + {0x00000624, 0x00000000, 0x09110609, REGSETALL}, + {0x00000628, 0x00000000, 0x442d0994, REGSETALL}, + {0x0000062c, 0x00000000, 0x271e102b, REGSETALL}, + {0x00000630, 0x00000000, 0x291b140a, REGSETALL}, + {0x00000634, 0x00000000, 0x001c0000, REGSETALL}, + {0x00000638, 0x00000000, 0x200f0f08, REGSETALL}, + {0x0000063c, 0x00000000, 0x29420a06, REGSETALL}, + {0x00000640, 0x00000000, 0x019e1fc1, REGSETALL}, + {0x00000644, 0x00000000, 0x10cb0196, REGSETALL}, + {0x00000648, 0x00000000, 0x00000000, REGSETALL}, + {0x0000064c, 0x00000000, 0x00082714, REGSETALL}, + {0x00000650, 0x00000000, 0x16442f0d, REGSETALL}, + {0x00000654, 0x00000000, 0x00001916, REGSETALL}, + {0x00000658, 0x00000000, 0x00000060, REGSETALL}, + {0x0000065c, 0x00000000, 0x00600020, REGSETALL}, + {0x00000660, 0x00000000, 0x00000000, REGSETALL}, + {0x00000680, 0x00000000, 0x0c00040f, REGSETALL}, + {0x00000684, 0x00000000, 0x03000604, REGSETALL}, + {0x00000688, 0x00000000, 0x0515040d, REGSETALL}, + {0x0000068c, 0x00000000, 0x20002c20, REGSETALL}, + {0x00000690, 0x00000000, 0x00140000, REGSETALL}, + {0x0000069c, 0x00000000, 0x01240074, REGSETALL}, + {0x000006a0, 0x00000000, 0x00000000, REGSETALL}, + {0x000006a4, 0x00000000, 0x202c0c00, REGSETALL}, + {0x000006a8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000004, 0x00000000, 0x30010036, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10010036, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x3002001b, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10010036, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30030031, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10030031, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x300b0066, (F_SET | REG4G)}, + {0x00000004, 0x00000000, 0x300b0036, (F_SET | REG8G)}, + {0x00000004, 0x00000000, 0x100b0066, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30160016, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10160016, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000410, 0x00000000, 0x00101010, REGSETALL}, + {0x00000420, 0x00000000, 0x0c181006, REGSETALL}, + {0x00000424, 0x00000000, 0x20200820, REGSETALL}, + {0x00000428, 0x00000000, 0x80000020, REGSETALL}, + {0x00000000, 0x00000000, 0x00000001, REGSETALL}, + {0x00000108, 0x00000000, 0x00003000, REGSETALL}, + {0x00000704, 0x00000000, 0x00000007, REGSETALL | OFFSET_SEL}, + {0x00000330, 0x00000000, 0x09313fff, (F_SET | REG4G | REG8G)}, + {0x00000330, 0x00000000, 0x09311fff, (F_SET | REG2G)}, + {0x00000508, 0x00000000, 0x00000033, (F_SET | REG4G | REG8G)}, + {0x00000508, 0x00000000, 0x00000013, (F_SET | REG2G)}, + {0x00000324, 0x00000000, 0x00002000, REGSETALL}, + {0x00000104, 0x00000000, 0x90000000, REGSETALL}, + {0x00000510, 0x00000000, 0x00000100, REGSETALL}, + {0x00000514, 0x00000000, 0x00000000, REGSETALL}, + {0x00000700, 0x00000000, 0x00000003, REGSETALL | OFFSET_SEL}, + {0x00000514, 0x00000000, 0x00000600, REGSETALL}, + {0x00000020, 0x00000000, 0x00000001, REGSETALL}, +}; + +static void ddr_csr_set(uintptr_t csrreg, uintptr_t secreg, const struct ddr_reg_cfg *data, + size_t len, u32 mask) +{ + for (size_t i = 0; i < len; i++) { + if (!(data[i].flag & mask)) + continue; + + uintptr_t addr; + if (data[i].flag & OFFSET_SEL) + addr = secreg + data[i].offset; + else + addr = csrreg + data[i].offset; + + if (data[i].flag & F_CLRSET) + DDR_REG_TRIGGER(addr, data[i].mask, data[i].val); + else + write32p(addr, data[i].val); + } +} + +static void ddrcsr_boot(uintptr_t csrreg, uintptr_t secreg, uintptr_t phyreg, size_t size) +{ + u32 mask; + + switch (size) { + case 2UL*GiB: + mask = REG2G; + break; + case 4UL*GiB: + mask = REG4G; + break; + case 8UL*GiB: + mask = REG8G; + break; + default: + return; + }; + + size_t len = ARRAY_SIZE(ddr_csr_cfg); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask); + + while (!(read32p(csrreg + 0x504) & BIT(31))) + ; + + write32p(csrreg + 0x504, 0x0); + write32p(csrreg + 0x50c, 0x0); + udelay(300); + write32p(csrreg + 0x50c, 0x1); + mdelay(3); + + switch (size) { + case 2UL*GiB: + write32p(csrreg + 0x10, 0x1c); + break; + case 4UL*GiB: + case 8UL*GiB: + write32p(csrreg + 0x10, 0x3c); + break; + default: + break; + }; + + write32p(csrreg + 0x14, 0x1); + udelay(4); + + len = ARRAY_SIZE(ddr_csr_cfg1); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask); + + udelay(4); + write32p(csrreg + 0x10, 0x11); + write32p(csrreg + 0x14, 0x1); + + switch (size) { + case 4UL*GiB: + case 8UL*GiB: + write32p(csrreg + 0x10, 0x20); + write32p(csrreg + 0x14, 0x1); + udelay(4); + write32p(csrreg + 0x10, 0x21); + write32p(csrreg + 0x14, 0x1); + break; + case 2UL*GiB: + default: + break; + }; + + write32p(csrreg + 0x514, 0x0); + while (!(read32p(csrreg + 0x518) & BIT(1))) + ; + + u32 val = read32p(csrreg + 0x518); + while ((val & 0x2) != 0x0) { + val = read32p(phyreg + 0x4); + + if ((val & 0x20) == 0x20) { + switch (val & 0x1f) { + case 0: /* ddrc_clock=12M */ + DDR_BUS_REG_SET(DDR_BUS_OSC_DIV2); + break; + case 1: /* ddrc_clock=200M */ + DDR_BUS_REG_SET(DDR_BUS_PLL1_DIV8); + break; + case 2: /* ddrc_clock=800M */ + DDR_BUS_REG_SET(DDR_BUS_PLL1_DIV2); + break; + default: + break; + }; + + write32p(phyreg + 0x8, 0x1); + while (read32p(phyreg + 0x8) & BIT(0)) + ; + } + + udelay(1); + val = read32p(csrreg + 0x518); + }; + + val = read32p(phyreg + 0x2000 + 0x14C); + val = read32p(phyreg + 0x2000 + 0x150); + write32p(phyreg + 0x2000 + 0x150, val & 0xF8000000); + + len = ARRAY_SIZE(ddr_csr_cfg2); + ddr_csr_set(phyreg + PHY_BASE_ADDR, secreg, ddr_csr_cfg2, len, mask); + + len = ARRAY_SIZE(ddr_csr_cfg3); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask); +} + +static const u32 ddr_phy_data[] = { + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 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+ 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 0x280, + 0x8000, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x800080, + 0x6e0080, + 0x1a00003, + 0x0, + 0x30000, + 0x80200, + 0x0, + 0x20202020, + 0x20202020, + 0x2020, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 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0x3f400000, + 0x3f3f1f3f, + 0x1f3f3f1f, + 0x1f3f3f, + 0x0, + 0x0, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x76543210, + 0x6010198, + 0x0, + 0x0, + 0x0, + 0x40700, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1142, + 0x3020100, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x300, + 0x300, + 0x300, + 0x300, + 0x2, + 0x4011, + 0x4011, + 0x40, + 0x40, + 0x4011, + 0x1fff00, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x1004011, + 0x200400, + +}; + +static void ddr_phy_util(uintptr_t phyreg) +{ + for (u32 i = 1792; i < ARRAY_SIZE(ddr_phy_data); i++) + write32p(phyreg + i * 4, ddr_phy_data[i]); + + for (u32 i = 0; i < 1792; i++) + write32p(phyreg + i * 4, ddr_phy_data[i]); +} + +static const u32 ddr_train_data[] = { + 0xb00, + 0x101, + 0x640000, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1, + 0x7, + 0x10002, + 0x300080f, + 0x1, + 0x5, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1010000, + 0x280a0000, + 0x0, + 0x1, + 0x3200000f, + 0x0, + 0x0, + 0x10102, + 0x1, + 0x0, + 0x0, + 0x0, + 0xaa, + 0x55, + 0xb5, + 0x4a, + 0x56, + 0xa9, + 0xa9, + 0xb5, + 0x1000000, + 0x1000000, + 0x0, + 0xf0f0000, + 0x14, + 0x7d0, + 0x300, + 0x0, + 0x0, + 0x1000000, + 0x10101, + 0x0, + 0x30000, + 0x100, + 0x170f, + 0x0, + 0x0, + 0x0, + 0xa140a01, + 0x204010a, + 0x2080510, + 0x40400, + 0x1000101, + 0x10100, + 0x2040f00, + 0x34000000, + 0x0, + 0x0, + 0x1000000, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10100, + 0x80101, + 0x2000200, + 0x1000100, + 0x1000000, + 0x2000200, + 0x200, + 0x0, + 0x0, + 0x0, + 0xe000004, + 0xc0d100f, + 0xa09080b, + 0x2010000, + 0x80103, + 0x200, + 0x0, + 0xf000000, + 0x4, + 0xa, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x30100, + 0x1010001, + 0x10200, + 0x4000103, + 0x1050001, + 0x10600, + 0x107, + 0x0, + 0x0, + 0x10001, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10000, + 0x4, + 0x0, + 0x10000, + 0x0, + 0x3c0003, + 0x80100a0, + 0x16, + 0x2c, + 0x33, + 0x20043, + 0x2000200, + 0x4, + 0x60c, + 0xa1400, + 0x280000, + 0x6, + 0x46, + 0x70, + 0x610, + 0x12b, + 0x4001035, + 0x1010404, + 0x1e01, + 0x1e001e, + 0x1000100, + 0x100, + 0x0, + 0x5060403, + 0x1011108, + 0x1010101, + 0xf0a0a, + 0x0, + 0x0, + 0x4000000, + 0x4021008, + 0x4020206, + 0xc0034, + 0x100038, + 0x17003f, + 0x10001, + 0x10001, + 0x10005, + 0x20064, + 0x100010b, + 0x60006, + 0x650100, + 0x1000065, + 0x10c010c, + 0x1e1a1e1a, + 0x1011e1a, + 0xa070601, + 0xa07060d, + 0x100b080d, + 0xc00f, + 0xc01000, + 0xc01000, + 0x21000, + 0x120005, + 0x190064, + 0x10b, + 0x1100, + 0x1e1a0056, + 0x6000101, + 0x130204, + 0x1e1a0058, + 0x1000101, + 0x230408, + 0x1e1a005e, + 0x9000101, + 0x610, + 0x4040800, + 0x40100, + 0x3000277, + 0xa032001, + 0xa0a, + 0x80908, + 0x901, + 0x1100315c, + 0xa062002, + 0xa0a, + 0x141708, + 0x150d, + 0x2d00838e, + 0xf102004, + 0xf0b, + 0x8c, + 0x578, + 0xc20, + 0x7940, + 0x206a, + 0x14424, + 0x730006, + 0x3030133, + 0x4, + 0x0, + 0x4, + 0x1, + 0x5, + 0x2, + 0x6, + 0x50, + 0x1, + 0x5, + 0x28, + 0x73, + 0xd6, + 0x1, + 0x5, + 0x6b, + 0x1000133, + 0x140040, + 0x10001, + 0x1900040, + 0x1000c, + 0x42b0040, + 0x320, + 0x360014, + 0x1010101, + 0x2020101, + 0x8080404, + 0x67676767, + 0x67676767, + 0x67676767, + 0x67676767, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x18171615, + 0x14131211, + 0x7060504, + 0x3020100, + 0x0, + 0x0, + 0x0, + 0x1000000, + 0x4020201, + 0x80804, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, +}; + +static void ddr_phy_train(uintptr_t phyreg) +{ + for (u32 i = 0; i < ARRAY_SIZE(ddr_train_data); i++) + write32p(phyreg + i * 4, ddr_train_data[i]); +} + +static const struct ddr_reg_cfg ddr_start_cfg[] = { + {0x00000164, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000138, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000564, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000538, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000964, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000938, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d64, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d38, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c04, 0xfffffeff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c04, 0xfffcffff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x000001f4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000198, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x000001a4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000170, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000178, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000180, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000164, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x000005f4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000598, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x000005a4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000570, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000578, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000580, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000564, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x000009f4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000998, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x000009a4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000970, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000978, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000980, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000964, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000df4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d98, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000da4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d70, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d78, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d80, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d64, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001d9c, 0xffffe000, 0x00001342, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001cac, 0xfffff0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c04, 0xfffffeff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x000000f8, 0xfffffeff, 0x00000000, REGCLRSETALL}, + {0x00000108, 0xfffffeff, 0x00000000, REGCLRSETALL}, + {0x00000298, 0xffffff80, 0x00000001, REGCLRSETALL}, + {0x000000f8, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {0x00000298, 0xffff80ff, 0x00000100, REGCLRSETALL}, + {0x000002cc, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {0x000002cc, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {0x00000298, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {0x00000298, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {0x000002d8, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {0x000002d8, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {0x0000029c, 0xffffff80, 0x00000017, REGCLRSETALL}, + {0x000000f8, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {0x0000029c, 0xffff80ff, 0x00001700, REGCLRSETALL}, + {0x000002e4, 0xff80ffff, 0x00200000, REGCLRSETALL}, + {0x0000010c, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {0x000002e4, 0x80ffffff, 0x20000000, REGCLRSETALL}, + {0x00000028, 0xffffffe0, 0x00000002, REGCLRSETALL}, + {0x00000000, 0xfffffffe, 0x00000001, REGCLRSETALL}, + {0x0000002c, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)}, + {0x000003dc, 0xffffffff, 0x00000008, REGCLRSETALL}, + {0x000003e4, 0xffffffff, 0x00000800, REGCLRSETALL}, + {0x000003f0, 0xffffffff, 0x00000008, REGCLRSETALL}, + {0x000003f8, 0xffffffff, 0x00000800, REGCLRSETALL}, + {0x00000464, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x000004c4, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x00000524, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x00000584, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x00000484, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x000004e4, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x00000544, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x000005a4, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x00000484, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x000004e4, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x00000544, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x000005a4, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x00000468, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x000004c8, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000528, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000588, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000488, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x000004e8, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000548, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x000005a8, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000468, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x000004c8, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000528, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000588, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000488, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x000004e8, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000548, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x000005a8, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000468, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x000004c8, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000528, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000588, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000488, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x000004e8, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000548, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x000005a8, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000104, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000504, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000904, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d04, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000180, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000580, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000980, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000d80, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000180, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000580, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000980, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d80, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000084, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000484, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000884, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c84, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001038, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001438, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001838, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000014c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000054c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000094c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d4c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001098, 0xf800ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001498, 0xf800ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001898, 0xf800ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001d90, 0xfffc0000, 0x00015547, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001d94, 0xfffc0000, 0x00000007, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001cf0, 0xffffe000, 0x0000007a, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001cf4, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c78, 0xffffffff, 0x000000ff, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001da0, 0xfffffc00, 0x000003d5, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000016c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000056c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000096c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d6c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001de0, 0x00000000, 0x0cc3bfc7, (OFFSET_SEL | REGSETALL)}, + {0x00001de4, 0x00000000, 0x0000ff8f, (OFFSET_SEL | REGSETALL)}, + {0x00001de8, 0x00000000, 0x033f07ff, (OFFSET_SEL | REGSETALL)}, + {0x00001dec, 0x00000000, 0x0c3c37ff, (OFFSET_SEL | REGSETALL)}, + {0x00001df0, 0x00000000, 0x1fffff10, (OFFSET_SEL | REGSETALL)}, + {0x00001df4, 0x00000000, 0x00230070, (OFFSET_SEL | REGSETALL)}, + {0x00001df8, 0x00000000, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)}, + {0x00001df8, 0x00000000, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)}, + {0x00001dfc, 0x00000000, 0x00000e10, (OFFSET_SEL | REGSETALL)}, + {0x00001e00, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e04, 0x00000000, 0x00188411, (OFFSET_SEL | REGSETALL)}, + {0x00001e08, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e0c, 0x00000000, 0x00180400, (OFFSET_SEL | REGSETALL)}, + {0x00001e10, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e14, 0x00000000, 0x00180400, (OFFSET_SEL | REGSETALL)}, + {0x00001e18, 0x00000000, 0x1fffffcf, (OFFSET_SEL | REGSETALL)}, + {0x00001e1c, 0x00000000, 0x00188400, (OFFSET_SEL | REGSETALL)}, + {0x00001e20, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e24, 0x00000000, 0x04188411, (OFFSET_SEL | REGSETALL)}, + {0x00001cb4, 0x00000000, 0x00024410, (OFFSET_SEL | REGSETALL)}, + {0x00001cc0, 0x00000000, 0x00024410, (OFFSET_SEL | REGSETALL)}, + {0x00001cc8, 0x00000000, 0x0002ffff, (OFFSET_SEL | REGSETALL)}, + {0x00000130, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000530, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000930, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d30, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000134, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000534, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000934, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d34, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001098, 0xffffff00, 0x000000ff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {0x00001498, 0xffffff00, 0x000000ff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {0x00001898, 0xffffff00, 0x000000ff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {0x00001098, 0xffffff00, 0x000000fb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {0x00001498, 0xffffff00, 0x000000fb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {0x00001898, 0xffffff00, 0x000000fb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {0x00001010, 0xffffffff, 0x01000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001410, 0xffffffff, 0x01000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001810, 0xffffffff, 0x01000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001ce0, 0x00000000, 0x03cf07f8, (OFFSET_SEL | REGSETALL)}, + {0x00001ce4, 0x00000000, 0x0000003f, (OFFSET_SEL | REGSETALL)}, + {0x00001ce8, 0x00000000, 0x001fffff, (OFFSET_SEL | REGSETALL)}, + {0x00001cec, 0x00000000, 0x00060000, (OFFSET_SEL | REGSETALL)}, + {0x00000208, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000608, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000a08, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000e08, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000020c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000060c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000a0c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000e0c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000074, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000474, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000874, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c74, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000078, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000478, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000878, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c78, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000007c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000047c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000087c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c7c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x000010bc, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x000014bc, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x000018bc, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c40, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001da0, 0xfff0ffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, +}; + +static void ddr_reg_set(uintptr_t reg, const struct ddr_reg_cfg *data, size_t len, u32 mask) +{ + for (size_t i = 0; i < len; i++) { + if (!(data[i].flag & mask)) + continue; + + uintptr_t addr; + if (data[i].flag & OFFSET_SEL) + addr = reg + PHY_AC_BASE_ADDR + data[i].offset; + else + addr = reg + PHY_BASE_ADDR + data[i].offset; + + if (data[i].flag & F_CLRSET) + DDR_REG_TRIGGER(addr, data[i].mask, data[i].val); + else if (data[i].flag & F_SET) + write32p(addr, data[i].val); + else + write32p(addr, read32p(addr) + data[i].val); + } +} + +static void ddr_phy_start(uintptr_t phyreg, size_t size) +{ + switch (size) { + case 2UL*GiB: + ddr_reg_set(phyreg, ddr_start_cfg, ARRAY_SIZE(ddr_start_cfg), REG2G); + break; + case 4UL*GiB: + ddr_reg_set(phyreg, ddr_start_cfg, ARRAY_SIZE(ddr_start_cfg), REG4G); + break; + case 8UL*GiB: + ddr_reg_set(phyreg, ddr_start_cfg, ARRAY_SIZE(ddr_start_cfg), REG8G); + break; + default: + die("unsupported DDR size\n"); + }; + + write32p(phyreg, 0x01); +} + +void sdram_init(size_t dram_size) +{ + printk(BIOS_DEBUG, "Initialize LPDDR4 memory\n"); + +#define JH7110_DDR_CTRL 0x15700000 +#define JH7110_DDR_PHY 0x13000000 + ddr_phy_train(JH7110_DDR_PHY + PHY_BASE_ADDR); + ddr_phy_util(JH7110_DDR_PHY + PHY_AC_BASE_ADDR); + ddr_phy_start(JH7110_DDR_PHY, 8UL*GiB); + + DDR_BUS_REG_SET(DDR_BUS_OSC_DIV2); + ddrcsr_boot(JH7110_DDR_CTRL, JH7110_DDR_CTRL + SEC_CTRL_ADDR, JH7110_DDR_PHY, dram_size); +} + +// sdram_init MUST be called before sdram_size +size_t sdram_size(void) +{ + //u64 devicepmp0 = read64((u64 *)FU740_PHYSICAL_FILTER); + //return ((devicepmp0 & 0xFFFFFFFFFFFFFF) << 2) - FU740_DRAM; + + return 8UL*GiB; //TODO get from register to account for all visionfive2 variations (e.g. 4 GB) +} + +#endif diff --git a/src/soc/starfive/jh7110/uart.c b/src/soc/starfive/jh7110/uart.c new file mode 100644 index 0000000..434c7d8 --- /dev/null +++ b/src/soc/starfive/jh7110/uart.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <console/uart.h> +#include <commonlib/bsd/helpers.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + if (idx < 2) + return JH7110_UART(idx); + else + return 0; +} + +unsigned int uart_platform_refclk(void) +{ + // peripheral clock is attached to UART subsystem + //return clock_get_pclk(); + return 24 * MHz; //TODO +} diff --git a/util/riscv/starfive-jh7110-spl-tool/.gitignore b/util/riscv/starfive-jh7110-spl-tool/.gitignore new file mode 100644 index 0000000..26c8888 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/.gitignore @@ -0,0 +1,10 @@ +_* +*.swp +*.o +*.out +*.key +*.diff +*.patch +*.out +tags +spl_tool diff --git a/util/riscv/starfive-jh7110-spl-tool/LICENSE b/util/riscv/starfive-jh7110-spl-tool/LICENSE new file mode 100644 index 0000000..36cc8c3 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/LICENSE @@ -0,0 +1,365 @@ +================================================================ + * Copyright 2018-2023 Shanghai StarFive Technology Co., Ltd. +================================================================ + +spl_tool license: + +Valid-License-Identifier: GPL-2.0 +Valid-License-Identifier: GPL-2.0-only +Valid-License-Identifier: GPL-2.0+ +Valid-License-Identifier: GPL-2.0-or-later +SPDX-URL: https://spdx.org/licenses/GPL-2.0.html +Usage-Guide: + To use this license in source code, put one of the following SPDX + tag/value pairs into a comment according to the placement + guidelines in the licensing rules documentation. + For 'GNU General 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/util/riscv/starfive-jh7110-spl-tool/Makefile b/util/riscv/starfive-jh7110-spl-tool/Makefile new file mode 100644 index 0000000..c6b4d9b --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ +override CFLAGS=-Wall -Wno-unused-result -Wno-format-truncation -O2 + +SRCS = $(wildcard *.c) +OBJS = $(SRCS:.c=.o) + +all: spl_tool + +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +spl_tool: $(OBJS) + $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@ + +clean: + rm -f *.o spl_tool diff --git a/util/riscv/starfive-jh7110-spl-tool/README.md b/util/riscv/starfive-jh7110-spl-tool/README.md new file mode 100644 index 0000000..e9f61e7 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/README.md @@ -0,0 +1,54 @@ +## DESCRIPTION + +spl_tool is a jh7110 signature tool used to generate spl header information and generate u-boot-spl.bin.normal.out. + +spl_tool can also fix the issue of emmc booting. + +## Prerequisites + +Install required additional packages: + +```bash +$ sudo apt-get install gcc make git +``` + +## Build + +just run `make` + +```bash +$ make +``` + +## Run + +usage + +```bash +$ ./spl_tool -h + + StarFive spl tool + +usage: +-c, --creat-splhdr creat spl hdr +-i, --fix-imghdr fixed img hdr for emmc boot. +-a, --spl-bak-addr set backup SPL addr(default: 0x200000) +-v, --version set version (default: 0x01010101) +-f, --file input file name(spl/img) +-h, --help show this information +``` + +Generate uboot-spl.bin.normal.out + +```bash +$./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin +ubsplhdr.sofs:0x240, ubsplhdr.bofs:0x200000, ubsplhdr.vers:0x1010101 name:$(Uboot_PATH)/spl/u-boot-spl.bin +SPL written to $(Uboot_PATH)/spl/u-boot-spl.bin.normal.out successfully. +``` + +Fix the emmc boot issue + +```bash +$ ./spl_tool -i -f sdcard.img +IMG sdcard.img fixed hdr successfully. +``` \ No newline at end of file diff --git a/util/riscv/starfive-jh7110-spl-tool/SOURCE b/util/riscv/starfive-jh7110-spl-tool/SOURCE new file mode 100644 index 0000000..4727b85 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/SOURCE @@ -0,0 +1 @@ +git@github.com:starfive-tech/Tools.git diff --git a/util/riscv/starfive-jh7110-spl-tool/crc32.c b/util/riscv/starfive-jh7110-spl-tool/crc32.c new file mode 100644 index 0000000..1394f97 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/crc32.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <sys/types.h> +#include <stdlib.h> +#include <stdint.h> + +static uint32_t crc32_reverse(uint32_t x) +{ + x = ((x & 0x55555555) << 1) | ((x >> 1) & 0x55555555); + x = ((x & 0x33333333) << 2) | ((x >> 2) & 0x33333333); + x = ((x & 0x0F0F0F0F) << 4) | ((x >> 4) & 0x0F0F0F0F); + x = (x << 24) | ((x & 0xFF00) << 8) | ((x >> 8) & 0xFF00) | (x >> 24); + return x; +} + +uint32_t crc32(uint32_t iv, uint32_t sv, const void *data, size_t n) +{ + const unsigned char *ptr; + unsigned x; + uint32_t byte, crc; + + crc = iv; + ptr = data; + while (n--) { + byte = *ptr++; + byte = crc32_reverse(byte); + for (x = 0; x < 8; x++, byte <<= 1) crc = ((crc ^ byte) & 0x80000000U) ? (crc << 1) ^ sv : (crc << 1); + } + + return crc; +} + +uint32_t crc32_final(uint32_t iv) +{ + return crc32_reverse(iv ^ ~0U); +} diff --git a/util/riscv/starfive-jh7110-spl-tool/spl_tool.c b/util/riscv/starfive-jh7110-spl-tool/spl_tool.c new file mode 100644 index 0000000..039e520 --- /dev/null +++ b/util/riscv/starfive-jh7110-spl-tool/spl_tool.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +#define _GNU_SOURCE +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <getopt.h> +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <stdbool.h> +#include <unistd.h> +#include <endian.h> +#include <errno.h> +#include <limits.h> + +#define NOSIZE ((size_t)-1) + +extern uint32_t crc32(uint32_t iv, uint32_t sv, const void *data, size_t n); +extern uint32_t crc32_final(uint32_t iv); + +/* all uint32_t ends up little endian in output header */ +struct __attribute__((__packed__)) ubootsplhdr { + uint32_t sofs; /* offset of spl header: 64+256+256 = 0x240 */ + uint32_t bofs; /* SBL_BAK_OFFSET: Offset of backup SBL from Flash info start (from input_sbl_normal.cfg) */ + uint8_t zro2[636]; + uint32_t vers; /* version: shall be 0x01010101 + * (from https://doc-en.rvspace.org/VisionFive2/SWTRM/VisionFive2_SW_TRM/create_spl.h...) */ + uint32_t fsiz; /* u-boot-spl.bin size in bytes */ + uint32_t res1; /* Offset from HDR to SPL_IMAGE, 0x400 (00 04 00 00) currently */ + uint32_t crcs; /* CRC32 of u-boot-spl.bin */ + uint8_t zro3[364]; +}; + +struct hdr_conf_t { + const char name[PATH_MAX]; + uint32_t vers; + uint32_t bofs; + bool creat_hdr_flag; + bool fixed_img_hdr_flag; +}; + +static struct ubootsplhdr ubsplhdr; +static struct ubootsplhdr imghdr; +static struct hdr_conf_t g_hdr_conf; + +static char ubootspl[181072-sizeof(struct ubootsplhdr)+1]; +static char outpath[PATH_MAX]; + +#define DEFVERSID 0x01010101 +#define DEFBACKUP 0x200000U +#define CRCFAILED 0x5A5A5A5A + +static void xerror(int errnoval, const char *s) +{ + if (errnoval) perror(s); + else fprintf(stderr, "%s\n", s); + exit(2); +} + +static void usage(void) +{ + const char help[] = { + "\n StarFive spl tool\n\n" + "usage:\n" + "-c, --creat-splhdr creat spl hdr\n" + "-i, --fix-imghdr fixed img hdr for emmc boot.\n" + "-a, --spl-bak-addr set backup SPL addr(default: 0x200000)\n" + "-v, --version set version (default: 0x01010101)\n" + "-f, --file input file name(spl/img)\n" + "-h, --help show this information\n" + }; + puts(help); +} + +static int parse_args(int argc, char **argv) +{ + uint32_t v; + + enum { + OPTION_CREAD_HDR = 1, + OPTION_FIXED_HDR, + OPTION_SBL_BAK_OFFSET, + OPTION_VERSION, + OPTION_FILENAME, + OPTION_HELP, + }; + + static struct option long_options[] = + { + {"creat-splhdr" , no_argument, NULL, OPTION_CREAD_HDR}, + {"fix-imghdr" , no_argument, NULL, OPTION_FIXED_HDR}, + {"spl-bak-addr" , required_argument, NULL, OPTION_SBL_BAK_OFFSET}, + {"version", required_argument, NULL, OPTION_VERSION}, + {"file", required_argument, NULL, OPTION_FILENAME}, + {"help", no_argument, NULL, OPTION_HELP}, + {0, 0, 0, 0} + }; + + while (1) + { + /* getopt_long stores the option index here. */ + int option_index = 0; + + int c = getopt_long(argc, argv, "cio:v:f:h", long_options, &option_index); + + /* Detect the end of the options. */ + if (c == -1) + break; + + switch (c) { + case 0: + /* If this option set a flag, do nothing else now. */ + if (long_options[option_index].flag != 0) + break; + + case 'c': + case OPTION_CREAD_HDR: + g_hdr_conf.creat_hdr_flag = true; + g_hdr_conf.fixed_img_hdr_flag = false; + break; + + case 'i': + case OPTION_FIXED_HDR: + g_hdr_conf.fixed_img_hdr_flag = true; + g_hdr_conf.creat_hdr_flag = false; + break; + + case 'a': + case OPTION_SBL_BAK_OFFSET: + v = (uint32_t)strtoul(optarg, NULL, 16); + v = htole32(v); + g_hdr_conf.bofs = v; + break; + + case 'v': + case OPTION_VERSION: + v = (uint32_t)strtoul(optarg, NULL, 16); + v = htole32(v); + g_hdr_conf.vers = v; + break; + + case 'f': + case OPTION_FILENAME: + strcpy((char*)g_hdr_conf.name, optarg); + break; + + case 'h': + case OPTION_HELP: + usage(); + break; + + default: + usage(); + break; + } + } + return 0; +} + +int spl_creat_hdr(struct hdr_conf_t *conf) +{ + int fd; + uint32_t v; + size_t sz; + + if (!conf->creat_hdr_flag) + return 0; + + ubsplhdr.sofs = htole32(0x240U); + ubsplhdr.res1 = htole32(0x400U); + ubsplhdr.bofs = conf->bofs ? conf->bofs : htole32(DEFBACKUP); + ubsplhdr.vers = conf->vers ? conf->vers : htole32(DEFVERSID); + + printf("ubsplhdr.sofs:%#x, ubsplhdr.bofs:%#x, ubsplhdr.vers:%#x name:%s\n", + ubsplhdr.sofs, ubsplhdr.bofs, ubsplhdr.vers, conf->name); + + fd = open(conf->name, O_RDONLY); + if (fd == -1) xerror(errno, conf->name); + + sz = (size_t)read(fd, ubootspl, sizeof(ubootspl)); + if (sz == NOSIZE) xerror(errno, conf->name); + if (sz >= (sizeof(ubootspl))) + xerror(0, "File too large! Please rebuild your SPL with -Os. Maximum allowed size is 180048 bytes."); + v = htole32((uint32_t)sz); + ubsplhdr.fsiz = v; + + close(fd); + snprintf(outpath, sizeof(outpath), "%s.normal.out", conf->name); + fd = creat(outpath, 0666); + if (fd == -1) xerror(errno, outpath); + + v = crc32(~0U, 0x04c11db7U, ubootspl, sz); + v = crc32_final(v); + v = htole32(v); + ubsplhdr.crcs = v; + + write(fd, &ubsplhdr, sizeof(struct ubootsplhdr)); + write(fd, ubootspl, sz); + + close(fd); + + printf("SPL written to %s successfully.\n", outpath); + + return 0; +} + +int img_fixed_hdr(struct hdr_conf_t *conf) +{ + int fd; + size_t sz; + + if (!conf->fixed_img_hdr_flag) + return 0; + + fd = open(conf->name, O_RDWR); + if (fd == -1) xerror(errno, conf->name); + + sz = (size_t)read(fd, &imghdr, sizeof(imghdr)); + if (sz == NOSIZE) xerror(errno, conf->name); + + /* When starting with emmc, bootrom will read 0x0 instead of partition 0. (Known issues). + Read GPT PMBR+Header, then write the backup address at 0x4, and write the wrong CRC + check value at 0x290, so that bootrom CRC check fails and jump to the backup address + to load the real spl. */ + + imghdr.bofs = conf->bofs ? conf->bofs : htole32(DEFBACKUP); + imghdr.crcs = htole32(CRCFAILED); + + lseek(fd, 0x0, SEEK_SET); + write(fd, &imghdr, sizeof(imghdr)); + close(fd); + + printf("IMG %s fixed hdr successfully.\n", conf->name); + + return 0; +} + +int main(int argc, char **argv) +{ + parse_args(argc, argv); + spl_creat_hdr(&g_hdr_conf); + img_fixed_hdr(&g_hdr_conf); +}