17 Mar
2019
17 Mar
'19
3:53 a.m.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31884 )
Change subject: soc/intel/cannonlake: Pass coreboot debug interface info to FSP ......................................................................
Patch Set 3:
Can you make use of BIT0 and store it in cbmem?
--
To view, visit https://review.coreboot.org/c/coreboot/+/31884
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c
Gerrit-Change-Number: 31884
Gerrit-PatchSet: 3
Gerrit-Owner: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com
Gerrit-Reviewer: Ronak Kanabar ronak.kanabar@intel.com
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: V Sowmya v.sowmya@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Patrick Georgi pgeorgi@google.com
Gerrit-Comment-Date: Sat, 16 Mar 2019 18:53:36 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment