Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195
-gerrit
commit 335a819c06c5927d20afc37e4d6a98138403f7d5 Author: Martin Roth gaumless@gmail.com Date: Sun Jan 11 14:58:47 2015 -0700
FSP platforms: Clear area in CAR for cbmem
cbmem requires that the memory at DCACHE_RAM_BASE be cleared or it does not get used.
This patch just clears CAR memory, leaving 4k untouched for stack. The stack is very small at this point, and obviously doesn't care whether the memory is cleared or not. The FSP has loaded a pattern into CAR, which helps to see the stack usage (and poisons the stack as well).
Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth gaumless@gmail.com --- src/mainboard/intel/cougar_canyon2/romstage.c | 3 +++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 2 ++ src/southbridge/intel/fsp_rangeley/romstage.c | 3 +++ 3 files changed, 8 insertions(+)
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 72832ea..e836bfa 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -180,6 +180,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) u32 pm1_cnt; u16 pm1_sts;
+ /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,CONFIG_DCACHE_RAM_SIZE - 0x1000); + post_code(0x40);
#if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b0b8133..8ba0886 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -158,6 +158,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t fd2_mask = 0;
+ /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,CONFIG_DCACHE_RAM_SIZE - 0x1000); post_code(0x40);
program_base_addresses(); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..62cb567 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -44,6 +44,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;
+ /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,CONFIG_DCACHE_RAM_SIZE - 0x1000); + /* * Do not use the Serial Console before it is setup. * This causes the I/O to clog and a side effect is