Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19665 )
Change subject: soc/intel/common: Add Intel PCIe common code ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/#/c/19665/1/src/soc/intel/common/block/pcie/pcie... File src/soc/intel/common/block/pcie/pcie.c:
PS1, Line 35:
can you use macro, i guess this is bit definition
Done.Revised to use macro for value representing cache line size.
PS1, Line 40: date_config16(d
why not use kconfig option for more debug pcie
Done
PS1, Line 61:
is that fix for all socs
Yes,for existing SOCs.Revised implementation and moved it to soc/Kconfig to provide provision to change,if it changes for upcoming SOCs.
PS1, Line 73: .read_resources
remove if not needed
Done