[coreboot-gerrit] Change in coreboot[master]: mb/google/primus: Correct SSD power sequence

[Casper Chang (Code Review)]

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59303 )

Change subject: mb/google/primus: Correct SSD power sequence
......................................................................

mb/google/primus: Correct SSD power sequence

SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PREST should be sequenced after power enable.

BUG=b:199967106
TEST=SSD was always discovered in warm/cold boot stress.

Signed-off-by: Casper Chang 
Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7
---
M src/mainboard/google/brya/variants/primus/gpio.c
1 file changed, 4 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59303/1

diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c
index c1dfee2..4c9434e 100644
--- a/src/mainboard/google/brya/variants/primus/gpio.c
+++ b/src/mainboard/google/brya/variants/primus/gpio.c
@@ -80,6 +80,8 @@
    PAD_CFG_GPO(GPP_A12, 1, DEEP),
    /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
    /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
    PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
    /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
@@ -117,16 +119,13 @@
    PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
    /* H13 : I2C7_SCL ==> EN_PP3300_SD */
    PAD_CFG_GPO(GPP_H13, 1, PLTRST),
-	/* B4  : PROC_GP3 ==> SSD_PERST_L
-	 * SSD_PERST_L is released after EN_PP3300_SSD is asserted; the
-	 * power rails take some time to come up.
-	 */
-	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 };

static const struct pad_config romstage_gpio_table[] = {
    /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
    PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
    /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
    PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };