[coreboot-gerrit] Change in coreboot[master]: [TESTME]sb/intel/nm10: Fix enabling HPET

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35758 )

Change subject: [TESTME]sb/intel/nm10: Fix enabling HPET
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[TESTME]sb/intel/nm10: Fix enabling HPET

RCBA_HPTC needs to be read back to consistently enable HPET.
This ought to fix raminit failing sometimes and SeaBIOS endlessly
waiting for user input.

TODO untested

Change-Id: I20a25fd97cd09fedb70469262c64d8d3828bb684
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/pineview/raminit.c
M src/southbridge/intel/i82801gx/lpc.c
2 files changed, 8 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/35758/1

diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 5cece41..7f59d91 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -552,10 +552,12 @@
 static void enable_hpet(void)
 {
    u32 reg32;
-	reg32 = RCBA32(0x3404);
+	reg32 = RCBA32(HPTC);
    reg32 &= ~0x3;
    reg32 |= (1 << 7);
-	RCBA32(0x3404) = reg32;
+	RCBA32(HPTC) = reg32;
+	/* On NM10 this only works if read back */
+	RCBA32(HPTC);
    HPET32(0x10) = HPET32(0x10) | 1;
 }

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 4e2f9f9..62576c1 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -310,6 +310,10 @@
    reg32 |= (1 << 7); // HPET Address Enable
    reg32 &= ~(3 << 0);
    RCBA32(HPTC) = reg32;
+	/* On NM10 this only works if read back */
+	RCBA32(HPTC);
+
+	write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
 }

static void enable_clock_gating(void)