[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold

[John Zhao (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Shreesh Chhabbi, Ravishankar Sarawadi, Tim Wawrzynczak, Shamile Khan, Patrick Rudolph, Divya S Sasidharan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43980

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold
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soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold

Update configuration for both of TCSS D3Hot and D3Cold. It is expected
D3Hot is enabled for all platforms. Because there are known limitations
for D3Cold enabling on pre-QS platform, this change reads cpu id and
disables D3Cold for pre-QS platform. For QS platform, D3Cold is
configured to be enabled.

BUG=None
TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0)
and enabled for QS (cpu:0x806c1).

Signed-off-by: John Zhao 
Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 10 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43980/4