Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61465 )
Change subject: sb/intel/i82801dx: Add call i8259_setup() ......................................................................
sb/intel/i82801dx: Add call i8259_setup()
Observed with aopen/dxplplusu that without SeaBIOS (using GRUB2 payload) Linux kernel panics.
< [ 0.000000] Using NULL legacy PIC < [ 0.000000] NR_IRQS: 2304, nr_irqs: 1024, preallocated irqs: 0 ... < [ 0.000000] unexpected #NM exception: ffff [#1] SMP PTI
versus
[ 0.000000] NR_IRQS: 2304, nr_irqs: 1024, preallocated irqs: 16
...
[ 0.004000] Enabling APIC mode: Flat. Using 3 I/O APICs [ 0.008000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0 [ 0.028000] tsc: Fast TSC calibration using PIT [ 0.032000] tsc: Detected 3198.436 MHz processor
Change-Id: I1beb93a8fd04697f259aefddfd369aa79e3359b7 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/61465 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/southbridge/intel/i82801dx/lpc.c 1 file changed, 5 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 34d93c4..bb38e1a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/io.h> +#include <arch/ioapic.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -8,8 +10,7 @@ #include <option.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> -#include <arch/io.h> -#include <arch/ioapic.h> +#include <pc80/i8259.h> #include "chip.h" #include "i82801dx.h"
@@ -273,6 +274,8 @@ /* Initialize the High Precision Event Timers */ enable_hpet(dev);
+ setup_i8259(); + /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */