[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake:[WIP] enable FSP-M compression

[Rizwan Qureshi (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63398 )

Change subject: soc/intel/alderlake:[WIP] enable FSP-M compression
......................................................................

soc/intel/alderlake:[WIP] enable FSP-M compression

FSP-M should be compressed to reduce its footprint in SPI NOR.
SinceLLC size in ADL systems in minimum of 6MB, the FSP-M can
be decompressed and executed from CAR. The patch contains following changes
* Enable FSP-M compression at build time
* Remove FSP_M_XIP as it will be executed from CAR instead of SPI
* Load and Rebase FSP-M to a newer safe address within CAR

Signed-off-by: Rizwan Qureshi 
Change-Id: Ie16e97b9445f2fe44b403bc03de55fbfb4de4da9
Signed-off-by: Rizwan Qureshi 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
2 files changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/63398/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 21b1767..7420fca 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -39,8 +39,8 @@
    select DISPLAY_FSP_VERSION_INFO
    select DRIVERS_USB_ACPI
    select FSP_COMPRESS_FSP_S_LZ4
+	select FSP_COMPRESS_FSP_M_LZ4
    select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
-	select FSP_M_XIP
    select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
    select FSP_USES_CB_DEBUG_EVENT_HANDLER
    select FSPS_HAS_ARCH_UPD
@@ -142,6 +142,10 @@
      The size of the cache-as-ram region required during bootblock
      and/or romstage.

+config FSP_M_ADDR
+	hex
+	default 0xfa100000
+
 config DCACHE_BSP_STACK_SIZE
    hex
    default 0xC0000
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index 095d210..82bf59c 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -60,6 +60,8 @@
 CPPFLAGS_common += -I$(src)/soc/intel/alderlake
 CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include

+$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
+
 ifeq ($(CONFIG_STITCH_ME_BIN),y)

$(eval $(call cse_add_dummy_to_bp1_bp2,DLMP))