[coreboot-gerrit] Change in ...coreboot[master]: arch/x86/smbios: Add type 7

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32131 )

Change subject: arch/x86/smbios: Add type 7
......................................................................

Patch Set 3:
> Patch Set 3:
> > Patch Set 3:
> >
> > Handle 0x0005, DMI type 7, 27 bytes
> > Cache Information
> >         Socket Designation: CACHE0
> >         Configuration: Enabled, Not Socketed, Level 1
> >         Operational Mode: Unknown
> >         Location: Internal
> >         Installed Size: 32 kB
> >         Maximum Size: 32 kB
> >         Supported SRAM Types:
> >                 Unknown
> >         Installed SRAM Type: Unknown
> >         Speed: Unknown
> >         Error Correction Type: Unknown
> >         System Type: Data
> >         Associativity: 8-way Set-associative
> >
> > Handle 0x0006, DMI type 7, 27 bytes
> > Cache Information
> >         Socket Designation: CACHE1
> >         Configuration: Enabled, Not Socketed, Level 1
> >         Operational Mode: Unknown
> >         Location: Internal
> >         Installed Size: 32 kB
> >         Maximum Size: 32 kB
> >         Supported SRAM Types:
> >                 Unknown
> >         Installed SRAM Type: Unknown
> >         Speed: Unknown
> >         Error Correction Type: Unknown
> >         System Type: Instruction
> >         Associativity: 8-way Set-associative
> >
> > Handle 0x0007, DMI type 7, 27 bytes
> > Cache Information
> >         Socket Designation: CACHE2
> >         Configuration: Enabled, Not Socketed, Level 2
> >         Operational Mode: Unknown
> >         Location: Internal
> >         Installed Size: 256 kB
> >         Maximum Size: 256 kB
> >         Supported SRAM Types:
> >                 Unknown
> >         Installed SRAM Type: Unknown
> >         Speed: Unknown
> >         Error Correction Type: Unknown
> >         System Type: Unified
> >         Associativity: 4-way Set-associative
> >
> > Handle 0x0008, DMI type 7, 27 bytes
> > Cache Information
> >         Socket Designation: CACHE3
> >         Configuration: Enabled, Not Socketed, Level 3
> >         Operational Mode: Unknown
> >         Location: Internal
> >         Installed Size: 8192 kB
> >         Maximum Size: 8192 kB
> >         Supported SRAM Types:
> >                 Unknown
> >         Installed SRAM Type: Unknown
> >         Speed: Unknown
> >         Error Correction Type: Unknown
> >         System Type: Unified
> >         Associativity: 16-way Set-associative
> >
> > From whiskeylake, I think the patch itself is already okay, but we may need to update the details
>
> Is it possible to query the unknown bits from hardware using CPUID or MSR? I couldn't find anything useful in the public documentation.

I am not able to find the report, the FSP code side just blindly report sram type as synchronous for all the caches