Attention is currently required from: Nico Huber, Tim Wawrzynczak, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 )
Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
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Patch Set 8:
(2 comments)
File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/37e6162d_fc5555e7
PS7, Line 396: bios_cntl &= ~SPI_BIOS_CONTROL_ASYNC_SS;
If we don't know if we are supposed to write 0 or 1, we can as […]
Looks like it's actually RO 😕
https://review.coreboot.org/c/coreboot/+/50754/comment/df52353a_894d7b0b
PS7, Line 403: }
A possible explanation: docs state that we must clear SYNC_SS before […]
I'll try to count how many iterations get executed.
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