Attention is currently required from: Paul Menzel. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58111 )
Change subject: mb/siemens/mc_ehl2: Update SPD for DDR4 devices ......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58111/comment/ba3b1564_38ba9df7 PS3, Line 9: devices
Are these the memory chips (“modules”). […]
I have added it.
https://review.coreboot.org/c/coreboot/+/58111/comment/cbe8d445_d2da739a PS3, Line 11:
As you are editing a hex file, what values/options are you changing? Where did you get these from? […]
Following values were adjusted according to this board characteristic and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules JEDEC Spec and the Specification for this Micron modules itself: SPD Byte 4 – only 4Gb density instead of 8Gb for mc_ehl1 SPD Byte 5 – different Row and Column Address Bits SPD Byte 29/30 – 4Gb LPDDR4 needs 130ns tRFCab SPD Byte 31/32 – 4Gb LPDDR4 needs 60ns tRFCpb
...and yes, with the mc_ehl1 settings the board didn’t boot.