[coreboot-gerrit] Change in coreboot[master]: mb/google, soc/intel: TEST Disable unused ports and TME

[ravindr1 (Code Review)]

Attention is currently required from: Sridhar Siricilla.
Hello Sridhar Siricilla,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/61492

to review the following change.

Change subject: mb/google, soc/intel: TEST Disable unused ports and TME
......................................................................

mb/google, soc/intel: TEST Disable unused ports and TME

Signed-off-by: Sridhar Siricilla 
Change-Id: I1f254df53c9fec117ee39d0c54e02116c4d7c103
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
4 files changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/61492/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index ee0fbce..585f418 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -22,6 +22,9 @@
    # Enable CNVi BT
    register "CnviBtCore" = "true"

+	#Enable Total Memory Encryption
+	register "enable_tme" = "true"
+
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
    register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 23071fe..ccf41e5 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -38,6 +38,9 @@
    register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
    register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port
    register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
+	register "enable_tme" = "0
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
@@ -69,6 +72,10 @@
    	},
    }"
    device domain 0 on
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+
    	device ref dtt on
    		chip drivers/intel/dptf
    			## sensor information
@@ -121,6 +128,7 @@
    			device generic 0 on end
    		end
    	end
+		device ref pcie_rp6 off end
    	device ref pcie_rp8 on
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a5543d6..24b3306 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -559,6 +559,11 @@
     * Default 0. Setting this to 1 enable CNVi DDR RFIM.
     */
    bool CnviDdrRfim;
+
+	/* Total Memory Encryption
+	 * Defaults to 0. Setting this to 1 to enable TME.
+	 */
+	bool enable_tme;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 790aa99..f030108 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -165,7 +165,7 @@
 {
    /* Disable BIOS Guard */
    m_cfg->BiosGuard = 0;
-	m_cfg->TmeEnable = CONFIG(INTEL_TME);
+	m_cfg->TmeEnable = config->enable_tme;
 }

static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,