Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45924 )
Change subject: nb/intel/sandybridge: Use `postcar_enable_tseg_cache` ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45924/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/memmap.c:
https://review.coreboot.org/c/coreboot/+/45924/2/src/northbridge/intel/sandy... PS2, Line 54: Cache the TSEG region using regular MTRRs. This is only useful : * when SMRRs are not supported, I don't think this is true. TSEG is sometimes used as a stage cache which implies that it is used before SMRR are set up. Also the postcar MTRR frame is only used upto the CPU init where more permanent MTRR's are used.