Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83075?usp=email )
Change subject: mb/google/nissa/var/nivviks: Enable wifi7 on pcie root port ......................................................................
mb/google/nissa/var/nivviks: Enable wifi7 on pcie root port
Enable pcie based, discreete wifi7 on root port4.
BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi7 module detection based on cbi settings
Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341 Signed-off-by: Poornima Tom poornima.tom@intel.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075 Reviewed-by: Eric Lai ericllai@google.com Reviewed-by: Kapil Porwal kapilporwal@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/brya/variants/nivviks/overridetree.cb 1 file changed, 24 insertions(+), 0 deletions(-)
Approvals: Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 4528016..22dd9ca 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -503,6 +503,30 @@ device generic 0 on end end end + device ref pcie_rp4 on + probe WIFI_CATEGORY WIFI_7 + # Enable WLAN Card PCIE 4 using clk 2 + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI_CATEGORY WIFI_7 + end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on + probe WIFI_CATEGORY WIFI_7 + end + end + end #PCIE4 WLAN card device ref pcie_rp7 on # Enable SD Card PCIe 7 using clk 3 register "pch_pcie_rp[PCH_RP(7)]" = "{