Hello Shaunak Saha, build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Paul Menzel, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Patrick Rudolph, V Sowmya, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42788
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Add CpuReplacementCheck to chip options
......................................................................
soc/intel/tigerlake: Add CpuReplacementCheck to chip options
Add CpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from devicetree.
This UPD allows platforms with soldered down SoC to skip CPU
replacement check to avoid a forced MRC traning.
TEST=boot and verified with volteer
Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42788/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Gerrit-Change-Number: 42788
Gerrit-PatchSet: 3
Gerrit-Owner: Jamie Ryu
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Gerrit-Reviewer: Angel Pons
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Gerrit-Reviewer: Srinidhi N Kaushik
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Gerrit-Reviewer: V Sowmya
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