Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52914 )
Change subject: soc/amd/cezanne: Populate PCI_INTR registers ......................................................................
soc/amd/cezanne: Populate PCI_INTR registers
This uses the new FSP PCI methods to pull the routing table and populate the pirq data structure.
BUG=b:184766519 TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/fch.c 2 files changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1d769be..dafc26f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_FSP_PCI select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 88265ab..028ffec 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -131,6 +131,12 @@ { /* Write PCI_INTR regs 0xC00/0xC01 */ write_pci_int_table(); + + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); }
/*