Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9218
-gerrit
commit c16ed3fd29f468ccc2163819c7db0587ac5da0b9 Author: Duncan Laurie dlaurie@chromium.org Date: Wed Oct 1 13:47:20 2014 -0700
broadwell: Disable ADSP power gating feature by default
Disable ADSP D3 and SRAM power gating features by default, and make the devicetree.cb flags into enable flags instead of disable.
BUG=chrome-os-partner:31588 BRANCH=samus,auron TEST=build and boot on samus
Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746 Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89 Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/220863 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/broadwell/adsp.c | 26 +++++++++++++++----------- src/soc/intel/broadwell/chip.h | 5 +++-- 2 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 9ecbe95..bf77763 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -69,21 +69,25 @@ static void adsp_init(struct device *dev)
/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0); - if (config->adsp_d3_pg_disable) { - if (pch_is_wpt()) { - tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; - tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; + if (pch_is_wpt()) { + if (config->adsp_d3_pg_enable) { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; + if (config->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; } else { - tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; - tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; + tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; } } else { - if (pch_is_wpt()) { - tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; - tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; - } else { + if (config->adsp_d3_pg_enable) { tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; - tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; + if (config->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; + } else { + tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; } } pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 005ab36..703c865 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -84,8 +84,9 @@ struct soc_intel_broadwell_config { uint8_t sio_i2c0_voltage; uint8_t sio_i2c1_voltage;
- /* Disable ADSP power gating in D3 */ - uint8_t adsp_d3_pg_disable; + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable;
/* * Clock Disable Map: