Attention is currently required from: Jérémy Compostella, Saurabh Mishra.
Hello Jérémy Compostella,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84174?usp=email
to look at the new patch set (#6).
Change subject: src/{incl/cpu, soc/intel/cmn}: Add Extended Feature Enable Register Macro
......................................................................
src/{incl/cpu, soc/intel/cmn}: Add Extended Feature Enable Register Macro
Details:
- Add (POWER_CTL) – Offset 1fc required bits.
- Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 1b2 required bits
Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b
Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com
---
M src/include/cpu/x86/msr.h
M src/soc/intel/common/block/include/intelblocks/msr.h
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84174/6
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Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b
Gerrit-Change-Number: 84174
Gerrit-PatchSet: 6
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