Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44391 )
Change subject: mb/intel/jslrvp: Correct PCI root port mapping ......................................................................
mb/intel/jslrvp: Correct PCI root port mapping
Jasper Lake SoC had PCI root port mapping swap, thats why we were using swapped mapping earlier for all the boards
Recently, patch was pushed to handle this swap in PCI enumeration code for Jasper Lake and we need to correct this mapping. Now this mapping aligns with actual port mapping in the schematics
BUG=None BRANCH=None TEST=NVMe and WLAN are getting detected after this changes
Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44391/1
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 1681b71..e205978 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -402,12 +402,12 @@
device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 - WLAN device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.4 on end # PCI Express Port 5 - NVMe + device pci 1c.5 of end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0