Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84115?usp=email )
Change subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c ......................................................................
soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c.
BUG=b:361728592 TEST=emerge-cherry coreboot
Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin yidilin@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jianjun Wang jianjun.wang@mediatek.com Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/Makefile.mk M src/soc/mediatek/mt8195/include/soc/pcie.h M src/soc/mediatek/mt8195/pcie.c 5 files changed, 15 insertions(+), 26 deletions(-)
Approvals: build bot (Jenkins): Verified Jianjun Wang: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index 0f02ab7..c34bc4e 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -22,5 +22,6 @@ void mtk_pcie_domain_read_resources(struct device *dev); void mtk_pcie_domain_set_resources(struct device *dev); void mtk_pcie_domain_enable(struct device *dev); +void mtk_pcie_reset(uintptr_t base_reg, bool enable);
#endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index 39714e1..e796dc1 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -247,6 +247,16 @@ pci_domain_set_resources(dev); }
+void mtk_pcie_reset(uintptr_t base_reg, bool enable) +{ + uint32_t flags = PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; + + if (enable) + setbits32p(base_reg + PCIE_RST_CTRL_REG, flags); + else + clrbits32p(base_reg + PCIE_RST_CTRL_REG, flags); +} + enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { if (!pci_root_bus()) @@ -291,7 +301,7 @@ printk(BIOS_WARNING, "%s: PCIe early init data not found, sleeping 100ms\n", __func__); - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(conf->base, true); } else { printk(BIOS_WARNING, "%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n", @@ -302,7 +312,7 @@ }
/* De-assert reset signals */ - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); + mtk_pcie_reset(conf->base, false);
if (!retry(100, (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 3446144..a37f715 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -13,7 +13,7 @@ bootblock-y += ../common/early_init.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/mmu_operations.c -bootblock-$(CONFIG_PCI) += pcie.c +bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h index 117f4cc..75c52c1 100644 --- a/src/soc/mediatek/mt8195/include/soc/pcie.h +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -6,7 +6,6 @@ #include <soc/pcie_common.h> #include <types.h>
-void mtk_pcie_reset(uintptr_t reg, bool enable); void mtk_pcie_pre_init(void);
bool mainboard_needs_pcie_init(void); diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index eb7ad87..2676207 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -9,11 +9,6 @@ #include <soc/pcie_common.h>
#define PCIE_REG_BASE_PORT0 0x112f0000 -#define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) -#define PCIE_MAC_RSTB BIT(0) -#define PCIE_PHY_RSTB BIT(1) -#define PCIE_BRG_RSTB BIT(2) -#define PCIE_PE_RSTB BIT(3)
struct pad_func { gpio_t gpio; @@ -46,28 +41,12 @@ } }
-void mtk_pcie_reset(uintptr_t reg, bool enable) -{ - uint32_t val; - - val = read32p(reg); - - if (enable) - val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB; - else - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB); - - write32p(reg, val); -} - void mtk_pcie_pre_init(void) { mtk_pcie_set_pinmux(0);
/* Assert all reset signals at early stage */ - mtk_pcie_reset(PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(PCIE_REG_BASE_PORT0, true);
early_init_save_time(EARLY_INIT_PCIE); }