[coreboot-gerrit] Change in coreboot[master]: [WIP]:gpp b2 for delbin and volteer and disable sdcard

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46648 )

Change subject: [WIP]:gpp b2 for delbin and volteer and disable sdcard
......................................................................

[WIP]:gpp b2 for delbin and volteer and disable sdcard

Signed-off-by: Kane Chen 
Change-Id: I79c7ab45769f91536da06860ff0b06db0af2851d
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/gpio.c
M src/mainboard/google/volteer/variants/delbin/gpio.c
3 files changed, 10 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46648/1

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 7486aef..097104a 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -89,12 +89,13 @@
    register "PcieRpLtrEnable[10]" = "1"
    register "HybridStorageMode" = "0"

-	# Enable SD Card PCIE 8 using clk 3
-	register "PcieRpEnable[7]" = "1"
-	register "PcieRpLtrEnable[7]" = "1"
-	register "PcieRpHotPlug[7]" = "1"
-	register "PcieClkSrcUsage[3]" = "7"
-	register "PcieClkSrcClkReq[3]" = "3"
+	# Disable SD Card PCIE 8 using clk 3
+	register "PcieRpEnable[7]" = "0"
+	register "PcieRpLtrEnable[7]" = "0"
+	register "PcieRpHotPlug[7]" = "0"
+	register "PcieClkSrcUsage[3]" = "0xff"
+ 
+

# Enable WLAN PCIE 7 using clk 1
    register "PcieRpEnable[6]" = "1"
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c
index 5d367e7..16749b5 100644
--- a/src/mainboard/google/volteer/variants/baseboard/gpio.c
+++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c
@@ -7,6 +7,9 @@
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */
 static const struct pad_config gpio_table[] = {
+
+	/* B2 : CPU_GP2 ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_B2, 1, DEEP),
    /* A0 thru A6 come configured out of reset, do not touch */
    /* A0  : ESPI_IO0 ==> ESPI_IO_0 */
    /* A1  : ESPI_IO1 ==> ESPI_IO_1 */
@@ -54,8 +57,6 @@
    PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
    /* B1  : CORE_VID1 */
    PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2  : VRALERT# ==> VRALERT_L */
-	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
    /* B3  : CPU_GP2 ==> NC */
    PAD_NC(GPP_B3, NONE),
    /* B4  : CPU_GP3 ==> NC */
diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c
index 5748bb3..f3e80cc 100644
--- a/src/mainboard/google/volteer/variants/delbin/gpio.c
+++ b/src/mainboard/google/volteer/variants/delbin/gpio.c
@@ -27,8 +27,6 @@
    /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
    PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),

-	/* B2  : VRALERT# ==> NC */
-	PAD_NC(GPP_B2, NONE),
    /* B9  : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
    PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
    /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */