[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIE in FSP

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
PS3, Line 208: 0
> Agreed, let's please add an option for this to `struct soc_intel_tigerlake_config` in the chip. […]

Well, if each bit corresponds to one PCI function, then we might as well check the corresponding devicetree devices and program this accordingly. Otherwise, the option would need to be manually kept in sync with the devicetree. I did something like that in CB:43128