Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP ......................................................................
Patch Set 5: Code-Review+1
(12 comments)
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 PS3, Line 7: PCIE
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: iIn
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: soc
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 PS3, Line 10: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 PS3, Line 11: Pcie
Will fix
Done
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 PS3, Line 18: this patch.
Will fix
Welp, Gerrit broke my lines... I've put clearer comments on the latest patchset.
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@10 PS5, Line 10: enablemen enablement
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@17 PS5, Line 17: the this fits on the previous line
https://review.coreboot.org/c/coreboot/+/42557/5//COMMIT_MSG@19 PS5, Line 19: this patch. this fits on the previous line
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 207: Pcie
PCIe
Done
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0
Thanks for the review. […]
Done