Attention is currently required from: Felix Singer, Bora Guvendik, Lijian Zhao, Shaunak Saha, Furquan Shaikh, Michael Niewöhner, Tim Wawrzynczak, Vaibhav Shankar, Aaron Durbin, Patrick Rudolph, Nico Huber, Martin Roth.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56662 )
Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/d31f4f60_5dc86582
PS1, Line 14:
Angel, yes, but only when setting some magic undocumented register. Intel claims it has *nothing* to do with C10/S0ix but it *must*. Setting PWRM_CIR30C=0x00 instantly breaks anything deeper PC3 (which is the default), setting it to 0x44 makes it work again.
I could also verify this on X11SSM-F (SKL/KBL), where vendor fw sets PWRM_CIR30C=0x44. I can break C10/S0ix by setting PWRM_CIR30C=0x00.
Alright, thanks for the info. I guess we can mark this as resolved?
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