[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
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Patch Set 74:

(6 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83635/comment/35c7cd47_23aa0ba7?usp... :
PS74, Line 49: PTL-U (15W) & PTL-H 12Xe (25W) SoC.
wondering on a client device, how is it possible to have two SoC integrated together ?

I guess what you are trying to say is like

```
Choose this option if the mainboard is built using either a PTL-U (15W) or PTL-H 12Xe (25W) system-on-a-chip (SoC).
```

https://review.coreboot.org/c/coreboot/+/83635/comment/8376b726_4066863d?usp... :
PS74, Line 55: 	select SOC_INTEL_PANTHERLAKE_BASE
```
depends on !SOC_INTEL_PANTHERLAKE_U_H
```

This will ensure any accidental selection of both Kconfig by any mainboard in future

https://review.coreboot.org/c/coreboot/+/83635/comment/a605c930_d1dbc8b0?usp... :
PS74, Line 116: if SOC_INTEL_PANTHERLAKE_U_H
you can drop this

File src/soc/intel/pantherlake/chip.h:

https://review.coreboot.org/c/coreboot/+/83635/comment/6d3c7752_312bf9ec?usp... :
PS74, Line 60: 1 << 0, 
do you wish to use BIT(0) here to maintain the parity with other macros ?

https://review.coreboot.org/c/coreboot/+/83635/comment/dbee50a7_b30cdb5a?usp... :
PS74, Line 60: //
also ```/* ... */```

https://review.coreboot.org/c/coreboot/+/83635/comment/5f23647c_ff64c032?usp... :
PS74, Line 162: 	enum {
              : 		IGD_SM_0MB = 0x00,
              : 		IGD_SM_32MB = 0x01,
              : 		IGD_SM_64MB = 0x02,
              : 		IGD_SM_96MB = 0x03,
              : 		IGD_SM_128MB = 0x04,
              : 		IGD_SM_160MB = 0x05,
              : 		IGD_SM_4MB = 0xF0,
              : 		IGD_SM_8MB = 0xF1,
              : 		IGD_SM_12MB = 0xF2,
              : 		IGD_SM_16MB = 0xF3,
              : 		IGD_SM_20MB = 0xF4,
              : 		IGD_SM_24MB = 0xF5,
              : 		IGD_SM_28MB = 0xF6,
              : 		IGD_SM_36MB = 0xF8,
              : 		IGD_SM_40MB = 0xF9,
              : 		IGD_SM_44MB = 0xFA,
              : 		IGD_SM_48MB = 0xFB,
              : 		IGD_SM_52MB = 0xFC,
              : 		IGD_SM_56MB = 0xFD,
              : 		IGD_SM_60MB = 0xFE,
              : 	} IgdDvmt50PreAlloc;
please confirm if this macro is relevant for PTL FSP or not ?