the following patch was just integrated into master: commit ef8deaffcbfb68c5b15cdc9c91607fce5734ec8b Author: Vaibhav Shankar vaibhav.shankar@intel.com Date: Tue Aug 23 17:56:17 2016 -0700
soc/intel/apollolake: Add PM methods to power gate PCIe
This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods.
BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional.
Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar vaibhav.shankar@intel.com Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net
See https://review.coreboot.org/16351 for details.
-gerrit