[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

[Kevin Chang (Code Review)]

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62919 )

Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
......................................................................

mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

GL9763e didn't support L0s state that disable L0s at root port.

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang 
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
3 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62919/1

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 75672ae..246f681 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -60,6 +60,7 @@
    	.vnn_sx_voltage_mv = 1250,
    }"
    register "tcss_aux_ori" = "1"
+	register "pcierpaspm[8]" = "2"
    register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
    register "sagv" = "SaGv_Enabled"

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a69e645..6432fa9 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -288,6 +288,7 @@
    struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
    struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
    uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
+	uint8_t pcierpaspm[CONFIG_MAX_PCH_ROOT_PORTS];

/* Gfx related */
    enum {
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 2f3027d..61adf9d 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -632,6 +632,7 @@
    	s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
    	s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
    	s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+		s_cfg->PcieRpAspm[i] = config->pcierpaspm[i];
    }
 }