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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )
Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
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Patch Set 24:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49766/comment/a7679c9c_28b4c8e4
PS9, Line 7: Disable S0i3.2 & S0i3.3 substates
:
: S0i3.2 and S0i3.3 are applicable only if wake on voice is
: disabled. As per Platform Design Guide, S0i3.2 and S0i3.3
: substates need to be disabled for Tigerlake.
Hi Furquan, what would be the right text to use for commit message?
Probably something like:
soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
This change uses the following information to determine the appropriate S0ix states to enable as per <reference doc/section #>:
1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH
In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document.
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