[coreboot-gerrit] [S] Change in coreboot[master]: nb/intel/i945: Use <commonlib/bsd/helpers.h> macros

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69406 )

Change subject: nb/intel/i945: Use <commonlib/bsd/helpers.h> macros
......................................................................

nb/intel/i945: Use <commonlib/bsd/helpers.h> macros

Change-Id: I2cbf7aaa31a560b0259ec763322045b34b479e23
Signed-off-by: Elyes Haouas 
---
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/memmap.c
M src/northbridge/intel/i945/northbridge.c
3 files changed, 25 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/69406/1

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 4818a73..b1f8efa 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -332,8 +332,8 @@
 void dump_spd_registers(u8 spd_map[4]);
 void sdram_dump_mchbar_registers(void);

-u32 decode_igd_memory_size(u32 gms);
-u32 decode_tseg_size(const u8 esmramc);
+size_t decode_igd_memory_size(u32 gms);
+size_t decode_tseg_size(const u8 esmramc);

/* Romstage mainboard callbacks */
 /* Optional: Override the default LPC config. */
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 1fa0358..321b387 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -5,6 +5,7 @@

#include <arch/romstage.h>
 #include <cbmem.h>
+#include <commonlib/bsd/helpers.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
@@ -14,17 +15,17 @@
 #include "i945.h"

/* Decodes TSEG region size to bytes. */
-u32 decode_tseg_size(const u8 esmramc)
+size_t decode_tseg_size(const u8 esmramc)
 {
    if (!(esmramc & 1))
    	return 0;
    switch ((esmramc >> 1) & 3) {
    case 0:
-		return 1 << 20;
+		return 1 * MiB;
    case 1:
-		return 2 << 20;
+		return 2 * MiB;
    case 2:
-		return 8 << 20;
+		return 8 * MiB;
    case 3:
    default:
    	die("Bad TSEG setting.\n");
@@ -64,14 +65,14 @@
 }

/* Decodes used Graphics Mode Select (GMS) to kilobytes. */
-u32 decode_igd_memory_size(const u32 gms)
+size_t decode_igd_memory_size(const u32 gms)
 {
-	static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64 };
+	static const size_t ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64 };

if (gms >= ARRAY_SIZE(ggc2uma))
    	die("Bad Graphics Mode Select (GMS) setting.\n");

-	return ggc2uma[gms] << 10;
+	return ggc2uma[gms] * KiB;
 }

void smm_region(uintptr_t *start, size_t *size)
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 3c5603c..651c3cf 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -14,7 +14,8 @@

static void mch_domain_read_resources(struct device *dev)
 {
-	uint32_t pci_tolm, tseg_sizek, cbmem_topk, delta_cbmem;
+	uint32_t pci_tolm, cbmem_topk, delta_cbmem;
+	size_t tseg_sizek;
    uint8_t tolud;
    uint16_t reg16;
    unsigned long long tomk, tomk_stolen;
@@ -41,9 +42,9 @@
    reg16 = pci_read_config16(d0f0, GGC);
    if (!(reg16 & 2)) {
    	printk(BIOS_DEBUG, "IGD decoded, subtracting ");
-		int uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
+		size_t uma_size = decode_igd_memory_size((reg16 >> 4) & 7);

-		printk(BIOS_DEBUG, "%dM UMA\n", uma_size / KiB);
+		printk(BIOS_DEBUG, "%ld UMA\n", uma_size / KiB);
    	tomk_stolen -= uma_size;

/* For reserving UMA memory in the memory map */
@@ -55,7 +56,7 @@
    }

tseg_sizek = decode_tseg_size(pci_read_config8(d0f0, ESMRAMC)) / KiB;
-	printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek / KiB);
+	printk(BIOS_DEBUG, "TSEG decoded, subtracting %ld\n", tseg_sizek / KiB);
    tomk_stolen -= tseg_sizek;
    tseg_memory_base = tomk_stolen * 1024ULL;
    tseg_memory_size = tseg_sizek * 1024ULL;