Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4138
-gerrit
commit 49cb209bd4b0cfe4020c7914a1dce3ad93ec7ec5 Author: Duncan Laurie dlaurie@chromium.org Date: Tue Apr 23 13:43:23 2013 -0700
lynxpoint: Rework LP GPIO handling
This adds some macros for the common GPIO defines and drops the gpio number definition from each entry. The end result is much easier to read. The wtm2 mainboard gpio list is modified to use this.
Also fix a bug in the LP version of get_gpio() that was always returning zero due to a miscompare.
Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e Signed-off-by: Duncan Laurie dlaurie@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/48946 Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/intel/wtm2/gpio.h | 439 +++++++----------------------- src/southbridge/intel/lynxpoint/lp_gpio.c | 18 +- src/southbridge/intel/lynxpoint/lp_gpio.h | 53 +++- 3 files changed, 156 insertions(+), 354 deletions(-)
diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h index 179259c..884fd66 100644 --- a/src/mainboard/intel/wtm2/gpio.h +++ b/src/mainboard/intel/wtm2/gpio.h @@ -22,348 +22,103 @@
#include "southbridge/intel/lynxpoint/lp_gpio.h"
-const struct pch_lp_gpio_map mainboard_gpio_map[] = { - /* LPSS_UART1_RXD */ - { .gpio = 0, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART1_TXD */ - { .gpio = 1, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART1_RTS_N_R */ - { .gpio = 2, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART1_CTS_N */ - { .gpio = 3, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C0_SDA_R */ - { .gpio = 4, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C0_SCL */ - { .gpio = 5, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C1_SDA */ - { .gpio = 6, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_I2C1_SCL */ - { .gpio = 7, - .conf0 = GPIO_MODE_NATIVE }, - /* NGFF_SLTA_WIFI_WAKE_N */ - { .gpio = 8, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* ACCEL_INT2_MCP (NGFF_SLTA_UART_WAKE_N) */ - { .gpio = 9, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* SMC_RUNTIME_SCI_N */ - { .gpio = 10, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_ACPI, - .route = GPIO_ROUTE_SCI }, - /* AMB_THRM_R_N */ - { .gpio = 11, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_LANPHY_ENABLE */ - { .gpio = 12, - .conf0 = GPIO_MODE_NATIVE }, - /* USB32_P0_PWREN */ - { .gpio = 13, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SH_INT_ACCEL_DRDY_USB_INT_N */ - { .gpio = 14, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* LAN_PWREN_N */ - { .gpio = 15, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* LAN_RST_N */ - { .gpio = 16, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* CRIT_TEMP_REP_R_N (NGFF_SLTB_CARD_PRESENT_SSD_N) */ - { .gpio = 17, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW }, - /* TBT_FORCE_PWR */ - { .gpio = 18, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* EC_IN_RW */ - { .gpio = 19, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE, - .owner = GPIO_OWNER_GPIO }, - /* CK_REQ_P2_NGFFSLTA_N_R */ - { .gpio = 20, - .conf0 = GPIO_MODE_NATIVE }, - /* CK_PCIE_LAN_REQ_N */ - { .gpio = 21, - .conf0 = GPIO_MODE_NATIVE }, - /* CK_REQ_P4_TBT_N */ - { .gpio = 22, - .conf0 = GPIO_MODE_NATIVE }, - /* CK_REQ_P5_N */ - { .gpio = 23, - .conf0 = GPIO_MODE_NATIVE }, - /* ME_PG_LED (NGFF_SLTB_WWN_CRD_PRSNT) */ - { .gpio = 24, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB_WAKEOUT_N */ - { .gpio = 25, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE }, - /* NFC_IRQ_MGP5 */ - { .gpio = 26, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* SMC_WAKE_SCI_N */ - { .gpio = 27, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE }, - /* PCH_NFC_RESET */ - { .gpio = 28, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* PCH_SLP_WLAN_N */ - { .gpio = 29, - .conf0 = GPIO_MODE_NATIVE }, - /* SUS_PWR_ACK_R */ - { .gpio = 30, - .conf0 = GPIO_MODE_NATIVE }, - /* AC_PRESENT_R */ - { .gpio = 31, - .conf0 = GPIO_MODE_NATIVE }, - /* PM_CKRUN_N */ - { .gpio = 32, - .conf0 = GPIO_MODE_NATIVE }, - /* SATA0_PHYSLP */ - { .gpio = 33, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* ESATA_DET_N */ - { .gpio = 34, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SATA_DIRECT_PRSNT_R_N */ - { .gpio = 35, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* NGFF_SSD_SATA2_PCIE1_DET_N */ - { .gpio = 36, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* NGFF_SSD_SATA3_PCIE0_DET_N */ - { .gpio = 37, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SATA1_PHYSLP_DIRECT */ - { .gpio = 38, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* SMC_EXTSMI_N_R */ - { .gpio = 39, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_ACPI, - .route = GPIO_ROUTE_SMI }, - /* USB_OC_0_1_R_N */ - { .gpio = 40, - .conf0 = GPIO_MODE_NATIVE }, - /* USB_OC_2_6_R_N */ - { .gpio = 41, - .conf0 = GPIO_MODE_NATIVE }, - /* TBT_CIO_PLUG_SMI_N_R */ - { .gpio = 42, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB32_P1_PWREN */ - { .gpio = 43, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SENSOR_HUB_RST_N */ - { .gpio = 44, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* GYRO_INT2_MCP_R (TBT_WAKE_Q_N) */ - { .gpio = 45, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SNSR_HUB_PWREN */ - { .gpio = 46, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SPI_TPM_HDR_IRQ_N */ - { .gpio = 47, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* PCIE_TBT_RST_N */ - { .gpio = 48, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* COMBO_JD */ - { .gpio = 49, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* TOUCH_PANEL_INTR_N */ - { .gpio = 50, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* PCH_WIFI_RF_KILL_N */ - { .gpio = 51, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* TOUCH_PNL_RST_N_R */ - { .gpio = 52, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SNSR_HUB_I2C_WAKE / ALS_INT_MCP (NGFF_SLTB_WWAN_SSD_DET2) */ - { .gpio = 53, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO }, - /* NGFF_SLTB_SSD_MC_WAKE_N */ - { .gpio = 54, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO }, - /* TOUCHPAD_INTR_N */ - { .gpio = 55, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, - .conf1 = GPIO_SENSE_ENABLE, - .owner = GPIO_OWNER_GPIO, - .irqen = GPIO_IRQ_ENABLE }, - /* NGFF_SLTB_WWAN_SSD_DET1 */ - { .gpio = 56, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* NGFF_SLTB_WWAN_PWREN */ - { .gpio = 57, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* SLATEMODE_HALLOUT_R */ - { .gpio = 58, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB2_CAM_PWREN */ - { .gpio = 59, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* USB_CR_PWREN_N */ - { .gpio = 60, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_SUS_STAT_N */ - { .gpio = 61, - .conf0 = GPIO_MODE_NATIVE }, - /* SUS_CK */ - { .gpio = 62, - .conf0 = GPIO_MODE_NATIVE }, - /* SLP_S5_R_N */ - { .gpio = 63, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_CLK_CMNHDR_R */ - { .gpio = 64, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_CMD_CMNHDR_R */ - { .gpio = 65, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D0_CMNHDR_R */ - { .gpio = 66, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D1_CMNHDR_R */ - { .gpio = 67, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D2_CMNHDR_R */ - { .gpio = 68, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_SDIO_D3_CMNHDR_R1 */ - { .gpio = 69, - .conf0 = GPIO_MODE_NATIVE }, - /* NGFF_SLTA_WIFI_PWREN_N_R (SDIO_POWER_EN) */ - { .gpio = 70, - .conf0 = GPIO_MODE_NATIVE }, - /* MPHY_PWREN */ - { .gpio = 71, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_BATLOW_R_N */ - { .gpio = 72, - .conf0 = GPIO_MODE_NATIVE }, - /* PCH_NOT_N */ - { .gpio = 73, - .conf0 = GPIO_MODE_NATIVE }, - /* SML1_DATA */ - { .gpio = 74, - .conf0 = GPIO_MODE_NATIVE }, - /* SML1_CK */ - { .gpio = 75, - .conf0 = GPIO_MODE_NATIVE }, - /* PCH_AUDIO_PWR_R */ - { .gpio = 76, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, - .conf1 = GPIO_SENSE_DISABLE }, - /* PC_SLTB_SSD_RST_N_R */ - { .gpio = 77, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* PM_EXTTS0_EC_N */ - { .gpio = 78, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* SIO1007_IRQ_N */ - { .gpio = 79, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* PM_EXTTS1_R_N */ - { .gpio = 80, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, - /* PCH_HDA_SPKR */ - { .gpio = 81, - .conf0 = GPIO_MODE_NATIVE }, - /* H_RCIN_N */ - { .gpio = 82, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_CS_R_N */ - { .gpio = 83, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_CLK_R */ - { .gpio = 84, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_MISO_R */ - { .gpio = 85, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI0_MOSI_BBS0_R */ - { .gpio = 86, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI1_CS_R_N */ - { .gpio = 87, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI1_CLK_R */ - { .gpio = 88, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_GSPI1_MISO_R */ - { .gpio = 89, - .conf0 = GPIO_MODE_NATIVE }, - /* NGFF_SLTA_WIFI_RST_N */ - { .gpio = 90, - .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, - .conf1 = GPIO_SENSE_DISABLE }, - /* LPSS_UART0_RXD */ - { .gpio = 91, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART0_TXD */ - { .gpio = 92, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART0_RTS_N */ - { .gpio = 93, - .conf0 = GPIO_MODE_NATIVE }, - /* LPSS_UART0_CTS_N */ - { .gpio = 94, - .conf0 = GPIO_MODE_NATIVE }, - /* END */ - { .gpio = GPIO_LIST_END } +static const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ + LP_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ + LP_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ + LP_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ + LP_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ + LP_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ + LP_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ + LP_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ + LP_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ + LP_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ + LP_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ + LP_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ + LP_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ + LP_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ + LP_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ + LP_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ + LP_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ + LP_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ + LP_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ + LP_GPIO_INPUT, /* 19: EC_IN_RW */ + LP_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ + LP_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ + LP_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ + LP_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ + LP_GPIO_OUT_LOW, /* 24: ME_PG_LED */ + LP_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ + LP_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ + LP_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ + LP_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ + LP_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ + LP_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ + LP_GPIO_NATIVE, /* 31: AC_PRESENT_R */ + LP_GPIO_NATIVE, /* 32: PM_CKRUN_N */ + LP_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ + LP_GPIO_INPUT, /* 34: ESATA_DET_N */ + LP_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ + LP_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ + LP_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ + LP_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ + LP_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ + LP_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ + LP_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ + LP_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ + LP_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ + LP_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ + LP_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ + LP_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ + LP_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ + LP_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ + LP_GPIO_INPUT, /* 49: COMBO_JD */ + LP_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ + LP_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ + LP_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ + LP_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ + LP_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ + LP_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ + LP_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ + LP_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ + LP_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ + LP_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ + LP_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ + LP_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ + LP_GPIO_NATIVE, /* 62: SUS_CK */ + LP_GPIO_NATIVE, /* 63: SLP_S5_R_N */ + LP_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ + LP_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ + LP_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ + LP_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ + LP_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ + LP_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ + LP_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ + LP_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ + LP_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ + LP_GPIO_NATIVE, /* 73: PCH_NOT_N */ + LP_GPIO_NATIVE, /* 74: SML1_DATA */ + LP_GPIO_NATIVE, /* 75: SML1_CK */ + LP_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ + LP_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ + LP_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ + LP_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ + LP_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ + LP_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ + LP_GPIO_NATIVE, /* 82: H_RCIN_N */ + LP_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ + LP_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ + LP_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ + LP_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ + LP_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ + LP_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ + LP_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ + LP_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ + LP_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ + LP_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ + LP_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ + LP_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ + LP_GPIO_END };
#endif diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 604423a..b90e5ba 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -45,19 +45,19 @@ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]) u32 irqen[3] = {0}; u32 reset[3] = {0}; u32 blink = 0; - int set, bit; + int set, bit, gpio = 0;
- for (config = map; config->gpio != GPIO_LIST_END; config++) { - if (config->gpio > MAX_GPIO_NUMBER) - continue; + for (config = map; config->conf0 != GPIO_LIST_END; config++, gpio++) { + if (gpio > MAX_GPIO_NUMBER) + break;
/* Setup Configuration registers 1 and 2 */ - outl(config->conf0, gpio_base + GPIO_CONFIG0(config->gpio)); - outl(config->conf1, gpio_base + GPIO_CONFIG1(config->gpio)); + outl(config->conf0, gpio_base + GPIO_CONFIG0(gpio)); + outl(config->conf1, gpio_base + GPIO_CONFIG1(gpio));
/* Determine set and bit based on GPIO number */ - set = config->gpio >> 5; - bit = config->gpio % 32; + set = gpio >> 5; + bit = gpio % 32;
/* Apply settings to set specific bits */ owner[set] |= config->owner << bit; @@ -83,7 +83,7 @@ int get_gpio(int gpio_num) { u16 gpio_base = get_gpio_base();
- if (gpio_num < MAX_GPIO_NUMBER) + if (gpio_num > MAX_GPIO_NUMBER) return 0;
return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 9666adc..48a23cb 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -36,7 +36,7 @@ #define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8))
#define MAX_GPIO_NUMBER 94 /* zero based */ -#define GPIO_LIST_END 0xff +#define GPIO_LIST_END 0xffffffff
/* conf0 */
@@ -54,8 +54,10 @@
#define GPI_LEVEL (1 << 30)
-#define GPO_LEVEL_LOW (0 << 31) -#define GPO_LEVEL_HIGH (1 << 31) +#define GPO_LEVEL_SHIFT 31 +#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_LOW (0 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_HIGH (1 << GPO_LEVEL_SHIFT)
/* conf1 */
@@ -91,6 +93,51 @@ #define GPIO_RESET_PWROK 0 #define GPIO_RESET_RSMRST 1
+#define LP_GPIO_END \ + { .conf0 = GPIO_LIST_END } + +#define LP_GPIO_NATIVE \ + { .conf0 = GPIO_MODE_NATIVE } + +#define LP_GPIO_UNUSED \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + .owner = GPIO_OWNER_GPIO, \ + .conf1 = GPIO_SENSE_DISABLE } + +#define LP_GPIO_ACPI_SCI \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ + .owner = GPIO_OWNER_ACPI, \ + .route = GPIO_ROUTE_SCI } + +#define LP_GPIO_ACPI_SMI \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + .owner = GPIO_OWNER_ACPI, \ + .route = GPIO_ROUTE_SMI } + +#define LP_GPIO_INPUT \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + .owner = GPIO_OWNER_GPIO } + +#define LP_GPIO_IRQ_EDGE \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \ + .owner = GPIO_OWNER_GPIO, \ + .irqen = GPIO_IRQ_ENABLE } + +#define LP_GPIO_IRQ_LEVEL \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \ + .owner = GPIO_OWNER_GPIO, \ + .irqen = GPIO_IRQ_ENABLE } + +#define LP_GPIO_OUT_HIGH \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \ + .owner = GPIO_OWNER_GPIO, \ + .conf1 = GPIO_SENSE_DISABLE } + +#define LP_GPIO_OUT_LOW \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \ + .owner = GPIO_OWNER_GPIO, \ + .conf1 = GPIO_SENSE_DISABLE } + struct pch_lp_gpio_map { u8 gpio; u32 conf0;