Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71678 )
Change subject: cpu/intel: Remove dummy _SPECIFIC_OPTIONS ......................................................................
cpu/intel: Remove dummy _SPECIFIC_OPTIONS
Change-Id: Iab6deede85c4f6095072a9e0813f70fc8de2c3ef Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_p/Kconfig 11 files changed, 33 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/71678/1
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index da7d1ab..97ad89b 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -1,11 +1,6 @@
config CPU_INTEL_HASWELL bool - -if CPU_INTEL_HASWELL - -config CPU_SPECIFIC_OPTIONS - def_bool y select ARCH_X86 select MMX select SSE2 @@ -20,6 +15,8 @@ select HAVE_ASAN_IN_ROMSTAGE select CPU_INTEL_COMMON_VOLTAGE
+if CPU_INTEL_HASWELL + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 5ff809f..24d636e 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_MODEL_2065X bool - -if CPU_INTEL_MODEL_2065X - -config CPU_SPECIFIC_OPTIONS - def_bool y select HAVE_EXP_X86_64_SUPPORT select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES @@ -17,6 +12,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE
+if CPU_INTEL_MODEL_2065X + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c168c9b..c5a7941 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_MODEL_206AX bool - -if CPU_INTEL_MODEL_206AX - -config CPU_SPECIFIC_OPTIONS - def_bool y select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT @@ -18,6 +13,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE
+if CPU_INTEL_MODEL_206AX + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index c30e066..4ba8747 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -2,11 +2,6 @@
config CPU_INTEL_SLOT_1 bool - -if CPU_INTEL_SLOT_1 - -config SLOT_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_65X select CPU_INTEL_MODEL_67X select CPU_INTEL_MODEL_68X @@ -19,6 +14,8 @@ select SETUP_XIP_CACHE select RESERVE_MTRRS_FOR_OS
+if CPU_INTEL_SLOT_1 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 2ff419b..f754290 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -1,14 +1,11 @@ config CPU_INTEL_SOCKET_441 bool - -if CPU_INTEL_SOCKET_441 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_106CX select MMX select SETUP_XIP_CACHE
+if CPU_INTEL_SOCKET_441 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 464a9b4..b279b4c 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,13 +1,10 @@ config CPU_INTEL_SOCKET_BGA956 bool - -if CPU_INTEL_SOCKET_BGA956 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_1067X select MMX
+if CPU_INTEL_SOCKET_BGA956 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index ed661b6..93a55a2 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -1,16 +1,13 @@ config CPU_INTEL_SOCKET_FCBGA559 bool + select CPU_INTEL_MODEL_106CX + select MMX + select CPU_HAS_L2_ENABLE_MSR help Select this socket on Intel Pineview
if CPU_INTEL_SOCKET_FCBGA559
-config SOCKET_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_MODEL_106CX - select MMX - select CPU_HAS_L2_ENABLE_MSR - config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 3c9f262..a47c4d0 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_SOCKET_LGA775 bool - -if CPU_INTEL_SOCKET_LGA775 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X @@ -12,6 +7,8 @@ select MMX select SIPI_VECTOR_IN_ROM
+if CPU_INTEL_SOCKET_LGA775 + config DCACHE_RAM_SIZE hex default 0x8000 # 32 kB diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 4e74eb4..322d76d 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -1,14 +1,11 @@ config CPU_INTEL_SOCKET_M bool - -if CPU_INTEL_SOCKET_M - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX select MMX
+if CPU_INTEL_SOCKET_M + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 12c8e37..0866b92 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,10 +1,5 @@ config CPU_INTEL_SOCKET_MPGA604 bool - -if CPU_INTEL_SOCKET_MPGA604 - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_F2X select MMX select UDELAY_TSC @@ -13,6 +8,8 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE
+if CPU_INTEL_SOCKET_MPGA604 + config DCACHE_RAM_BASE hex default 0xfefc0000 diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index e90b42a..552ed70 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -1,14 +1,11 @@ config CPU_INTEL_SOCKET_P bool - -if CPU_INTEL_SOCKET_P - -config SOCKET_SPECIFIC_OPTIONS - def_bool y select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX select MMX
+if CPU_INTEL_SOCKET_P + config DCACHE_RAM_BASE hex default 0xfefc0000